专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120257456A1 SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE METHOD THEREOF 有权
标题翻译：半导体存储器件及其数据写入方法
公开(公告)号：US20120257456A1
公开(公告)日：2012-10-11
申请号：US13525978
申请日：2012-06-18
申请人： Yukio KOMATSU
发明人： Yukio KOMATSU
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3459 , G11C2211/5621
摘要： A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other threshold voltage levels. The control circuit determines whether a verify pass bit number of the lowest threshold voltage level, which is counted by a bit scan circuit, is a prescribed bit number or more, and the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels.
摘要翻译：半导体存储器件包括控制电路。控制电路执行控制，以在数据写入操作时仅对存储单元的最低阈值电压电平执行验证操作，并且跳过相对于其它阈值电压电平的验证操作。控制电路确定由位扫描电路计数的最低阈值电压电平的验证通过位数是否为规定位数或更多，并且如果验证通过位数为规定的位数以上，仅对最低阈值电压电平和高于最低阈值电压电平的阈值电压电平进行验证操作，并且跳过关于其它阈值电压电平的验证操作。

2. 发明授权

US07948804B2 Semiconductor memory device and data write method thereof 有权
标题翻译：半导体存储器件及其数据写入方法
公开(公告)号：US07948804B2
公开(公告)日：2011-05-24
申请号：US12535040
申请日：2009-08-04
申请人： Yukio Komatsu
发明人： Yukio Komatsu
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3459 , G11C2211/5621
摘要： A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other threshold voltage levels. The control circuit determines whether a verify pass bit number of the lowest threshold voltage level, which is counted by a bit scan circuit, is a prescribed bit number or more, and the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels.
摘要翻译：半导体存储器件包括控制电路。控制电路执行控制，以在数据写入操作时仅对存储单元的最低阈值电压电平执行验证操作，并且跳过相对于其它阈值电压电平的验证操作。控制电路确定由位扫描电路计数的最低阈值电压电平的验证通过位数是否为规定位数或更多，并且如果验证通过位数为规定的位数以上，仅对最低阈值电压电平和高于最低阈值电压电平的阈值电压电平进行验证操作，并且跳过关于其它阈值电压电平的验证操作。

3. 发明授权

US5942176A Methods of and agents for lubricating synthetic fibers 失效
标题翻译：润滑合成纤维的方法和试剂
公开(公告)号：US5942176A
公开(公告)日：1999-08-24
申请号：US996114
申请日：1997-12-22
申请人： Tsukasa Fujii , Michiharu Nagai , Yukio Komatsu , Yasushi Maeshima
发明人： Tsukasa Fujii , Michiharu Nagai , Yukio Komatsu , Yasushi Maeshima
IPC分类号： D06M13/07 , C08G63/664 , D01D5/096 , D01F11/04 , D06M13/02 , D06M13/325 , D06M13/328 , D06M15/507 , D06M15/53 , D06M101/00 , D06M101/12 , D06M101/16
CPC分类号： D06M15/53 , D06M15/507 , D06M7/00 , D06M2200/40
摘要： Synthtic fibers can be effectively lubricated by applying a lubricant containing polyether polyester block copolymer shown as follows: ##STR1## where X, Z, A.sup.1, Y.sup.1, and R.sup.1 are each of a specified structure and integers a, b, c, p and q satisfy certain conditions.
摘要翻译：合成纤维可以通过涂布含有如下聚醚聚酯嵌段共聚物的润滑剂而被有效地润滑：其中X，Z，A1，Y1和R1各自为特定结构，并且整数a，b，c，p和q满足某些条件。

4. 发明授权

US5646616A Picking system 失效
标题翻译：采摘系统
公开(公告)号：US5646616A
公开(公告)日：1997-07-08
申请号：US494983
申请日：1995-06-26
申请人： Yukio Komatsu
发明人： Yukio Komatsu
IPC分类号： B65G1/137 , G08G1/123
CPC分类号： B65G1/1375 , G06Q20/203 , B65G2209/04 , B65G2209/06
摘要： To display picking information on a liquid crystal display unit, ID tags are disposed at the entrance and the exits of paths between racks, and the current position of a picking cart is recognized by way of communication with an antenna. Between an entrance and an exit, the distance over which the picking cart has traveled from the communication position with an ID tag is detected by way of an encoder which detects rotation of a wheel of the picking cart to recognize the current position.
摘要翻译：为了在液晶显示单元上显示拾取信息，ID标签设置在机架之间的入口和出口处，并且通过与天线的通信来识别拾取车的当前位置。在入口和出口之间，通过用于检测拾取车的车轮的旋转以识别当前位置的编码器来检测拾取车已经从具有ID标签的通信位置行进的距离。

5. 发明授权

US4855656A Driverless car travelling guide system 失效
标题翻译：无人驾驶车导游系统
公开(公告)号：US4855656A
公开(公告)日：1989-08-08
申请号：US82441
申请日：1987-08-06
申请人： Yoshihiro Saitoh , Minoru Kondoh , Yukio Komatsu
发明人： Yoshihiro Saitoh , Minoru Kondoh , Yukio Komatsu
IPC分类号： G05D1/02
CPC分类号： G05D1/0265 , G05D2201/0216 , Y02T10/7258
摘要： An electroconductive guide line is laid along a travelling path of a driverless car on the ground side, while on the driverless car side are provided a means for inducing electromotive force in the guide line and a means for detecting a magnetic field created upon generation of an electric current in the guide line.
摘要翻译：导电引导线沿着地面侧的无人驾驶车的行进路径铺设，而在无驾驶室侧设置有用于在引导线中感应电动势的装置，以及用于检测在产生电动势时产生的磁场的装置导线中的电流。

6. 发明授权

US08223557B2 Semiconductor memory device and data write method thereof 有权
标题翻译：半导体存储器件及其数据写入方法
公开(公告)号：US08223557B2
公开(公告)日：2012-07-17
申请号：US13099962
申请日：2011-05-03
申请人： Yukio Komatsu
发明人： Yukio Komatsu
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3459 , G11C2211/5621
摘要： A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other threshold voltage levels. The control circuit determines whether a verify pass bit number of the lowest threshold voltage level, which is counted by a bit scan circuit, is a prescribed bit number or more, and the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels.
摘要翻译：半导体存储器件包括控制电路。控制电路执行控制以在数据写入操作时仅对存储单元的最低阈值电压电平执行验证操作，并且跳过相对于其它阈值电压电平的验证操作。控制电路确定由位扫描电路计数的最低阈值电压电平的验证通过位数是否为规定的位数或更多，并且如果验证通过位数为规定的位数以上，仅对最低阈值电压电平和高于最低阈值电压电平的阈值电压电平进行验证操作，并且跳过关于其他阈值电压电平的验证操作。

7. 发明申请

US20110205807A1 SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE METHOD THEREOF 有权
标题翻译：半导体存储器件及其数据写入方法
公开(公告)号：US20110205807A1
公开(公告)日：2011-08-25
申请号：US13099962
申请日：2011-05-03
申请人： Yukio KOMATSU
发明人： Yukio KOMATSU
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3459 , G11C2211/5621
摘要： A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other threshold voltage levels. The control circuit determines whether a verify pass bit number of the lowest threshold voltage level, which is counted by a bit scan circuit, is a prescribed bit number or more, and the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels.
摘要翻译：半导体存储器件包括控制电路。控制电路执行控制，以在数据写入操作时仅对存储单元的最低阈值电压电平执行验证操作，并且跳过相对于其它阈值电压电平的验证操作。控制电路确定由位扫描电路计数的最低阈值电压电平的验证通过位数是否为规定位数或更多，并且如果验证通过位数为规定的位数以上，仅对最低阈值电压电平和高于最低阈值电压电平的阈值电压电平进行验证操作，并且跳过关于其它阈值电压电平的验证操作。

8. 发明授权

US07807545B2 Method for manufacturing SIMOX wafer 失效
标题翻译：制造SIMOX晶圆的方法
公开(公告)号：US07807545B2
公开(公告)日：2010-10-05
申请号：US11670636
申请日：2007-02-02
申请人： Yoshiro Aoki , Yukio Komatsu , Tetsuya Nakai , Seiichi Nakamura
发明人： Yoshiro Aoki , Yukio Komatsu , Tetsuya Nakai , Seiichi Nakamura
IPC分类号： H01L21/76 , H01L21/265 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76243
摘要： A SIMOX wafer having a BOX layer with a thin film thickness is obtained without a reduction in productivity or deterioration in quality. In a method for manufacturing a SIMOX wafer comprising: a step of forming a first ion-implanted layer in a silicon wafer; a step of forming a second ion-implanted layer that is in an amorphous state; and a high-temperature heat treatment step of maintaining the wafer in an oxygen contained atmosphere at a temperature that is not lower than 1300° C. but less than a silicon melting point for 6 to 36 hours to change the first and the second ion-implanted layers into a BOX layer, a gas containing chlorine that is not less than 0.1 volume % but less than 1.0 volume % is mixed into an atmosphere during temperature elevation in the high-temperature heat treatment.
摘要翻译：获得具有薄膜厚度的BOX层的SIMOX晶片，而不会降低生产率或质量劣化。一种用于制造SIMOX晶片的方法，包括：在硅晶片中形成第一离子注入层的步骤; 形成处于非晶态的第二离子注入层的步骤; 以及将晶片保持在含氧气氛中的不低于1300℃但小于硅熔点6〜36小时的高温热处理步骤，以改变第一和第二离子交换树脂，将注入层置于BOX层中，在高温热处理的升温过程中将含有不少于0.1体积％但小于1.0体积％的氯的气体混入大气中。

9. 发明申请

US20070238269A1 Method for Manufacturing Simox Wafer and Simox Wafer Obtained by This Method 失效
标题翻译：通过该方法获得的Simox晶圆和Simox晶圆的制造方法
公开(公告)号：US20070238269A1
公开(公告)日：2007-10-11
申请号：US11695706
申请日：2007-04-03
申请人： Yoshiro Aoki , Riyuusuke Kasamatsu , Yukio Komatsu
发明人： Yoshiro Aoki , Riyuusuke Kasamatsu , Yukio Komatsu
IPC分类号： H01L21/20
CPC分类号： H01L21/76243
摘要： It is an object of the present invention to provide a method for manufacturing SIMOX wafer, wherein roughness Rms of a measurement area of 10 square micrometers in a surface of an SOI layer and roughness Rms of a measurement area of 10 square micrometers in an interface between the SOI layer and a BOX layer can be reduced respectively and a SIMOX obtained by the method. The method is to manufacture a SIMOX wafer comprising; a step of forming a first ion-implanted layer 12 containing highly concentrated oxygen within a wafer 11; a step of forming a second ion-implanted amorphous layer 13; and a high temperature heat treatment step of transforming the first and second ion-implanted layers into a BOX layer 15 by holding the wafer at a temperature between 1300° C. or more and a temperature less than a silicon melting point in an atmosphere containing oxygen, wherein when a first dose amount in the step of forming the first ion-implanted layer is set to 2×1017 to 3×1017 atoms/cm2, the first implantation energy is set to 165 to 240 keV and a second dose amount in the step of forming the second ion-implanted layer is set to 1×1014 to 1×1016 atoms/cm2.
摘要翻译：本发明的目的是提供一种制造SIMOX晶片的方法，其中在SOI层的表面上的测量面积为10平方微米的粗糙度Rms和在10μm的界面上的测量面积为10平方微米的粗糙度Rms 可以分别降低SOI层和BOX层，并通过该方法获得SIMOX。该方法是制造SIMOX晶片，其包括：在晶片11内形成含有高浓度氧的第一离子注入层12的步骤; 形成第二离子注入非晶层13的步骤; 以及高温热处理步骤，通过将晶片保持在含有氧气的气氛中在1300℃以上的温度和小于硅熔点的温度下，将第一和第二离子注入层转变成BOX层15 其中当形成第一离子注入层的步骤中的第一剂量设定为2×10 17至3×10 17原子/ cm 2时， >，将第一注入能量设定为165至240keV，并且在形成第二离子注入层的步骤中的第二剂量设定为1×10 14至1×10 16 >原子/ cm 2。

10. 发明申请

US20050098803A1 Semiconductor device having fuses 失效
标题翻译：具有保险丝的半导体器件
公开(公告)号：US20050098803A1
公开(公告)日：2005-05-12
申请号：US10941030
申请日：2004-09-15
申请人： Yukio Komatsu , Hajime Koyama
发明人： Yukio Komatsu , Hajime Koyama
IPC分类号： H01L21/3205 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L23/525 , H01L27/04 , H01L27/10 , H01L27/108 , H01L29/768
CPC分类号： H01L23/5258 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device which includes fuses for relieving defective areas in the semiconductor device is described. There is provided a semiconductor device including a semiconductor substrate having a circuit element, an insulating layer provided on the semiconductor substrate, a fuse element formed in the insulating layer, the fuse element including at least two fuse units connected in series, each of the fuse units having a resistor and a fuse connected in parallel, the fuse disposed above the resistor.
摘要翻译：描述了包括用于缓解半导体器件中的缺陷区域的熔丝的半导体器件。提供了一种半导体器件，包括具有电路元件的半导体衬底，设置在半导体衬底上的绝缘层，形成在绝缘层中的熔丝元件，熔丝元件包括串联连接的至少两个熔丝单元，每个保险丝具有电阻器和熔丝并联的单元，熔丝设置在电阻器上方。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式