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1. 发明授权

US09183910B2 Semiconductor memory devices for alternately selecting bit lines 有权
标题翻译：用于交替选择位线的半导体存储器件
公开(公告)号：US09183910B2
公开(公告)日：2015-11-10
申请号：US13907223
申请日：2013-05-31
申请人： Yun-Sang Lee , Dong-Seok Kang , Sang-Beom Kang , Chan-Kyung Kim , Chul-Woo Park , Dong-Hyun Sohn , Hyung-Rok Oh
发明人： Yun-Sang Lee , Dong-Seok Kang , Sang-Beom Kang , Chan-Kyung Kim , Chul-Woo Park , Dong-Hyun Sohn , Hyung-Rok Oh
IPC分类号： G11C11/16 , G11C7/12
CPC分类号： G11C11/1653 , G11C7/12 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/1697
摘要： A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).
摘要翻译：半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和对多个STT-MRAM单元进行写入操作。该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号）。

2. 发明申请

US20150221615A1 STACKED SEMICONDUCTOR APPARATUS, SYSTEM AND METHOD OF FABRICATION 审中-公开
公开(公告)号：US20150221615A1
公开(公告)日：2015-08-06
申请号：US14683195
申请日：2015-04-10
申请人： KI-TAE PARK , KANG-WOOK LEE , YOUNG-DON CHOI , YUN-SANG LEE
发明人： KI-TAE PARK , KANG-WOOK LEE , YOUNG-DON CHOI , YUN-SANG LEE
IPC分类号： H01L25/065 , H01L23/00
CPC分类号： H01L25/0657 , G11C5/06 , H01L23/34 , H01L23/5384 , H01L23/64 , H01L24/17 , H01L2224/16 , H01L2224/1712 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2225/06589 , H01L2225/1058 , H01L2924/09701 , H01L2924/14 , H01L2924/1434 , H01L2924/19106 , H01L2924/00
摘要： A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

3. 发明申请

US20130077374A1 STACKED SEMICONDUCTOR APPARATUS, SYSTEM AND METHOD OF FABRICATION 审中-公开
公开(公告)号：US20130077374A1
公开(公告)日：2013-03-28
申请号：US13659146
申请日：2012-10-24
申请人： Ki-Tae PARK , Kang-Wook LEE , Young-Don CHOI , Yun-Sang LEE
发明人： Ki-Tae PARK , Kang-Wook LEE , Young-Don CHOI , Yun-Sang LEE
IPC分类号： H01L23/538 , G11C5/06 , H01L23/34
CPC分类号： H01L25/0657 , G11C5/06 , H01L23/34 , H01L23/5384 , H01L23/64 , H01L24/17 , H01L2224/16 , H01L2224/1712 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2225/06589 , H01L2225/1058 , H01L2924/09701 , H01L2924/14 , H01L2924/1434 , H01L2924/19106 , H01L2924/00
摘要： A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

4. 发明申请

US20090180257A1 STACKED SEMICONDUCTOR APPARATUS, SYSTEM AND METHOD OF FABRICATION 审中-公开
标题翻译：堆叠半导体装置，制造方法和制造方法
公开(公告)号：US20090180257A1
公开(公告)日：2009-07-16
申请号：US12352735
申请日：2009-01-13
申请人： Ki-Tae PARK , Kang-Wook LEE , Young-Don CHOI , Yun-Sang LEE
发明人： Ki-Tae PARK , Kang-Wook LEE , Young-Don CHOI , Yun-Sang LEE
IPC分类号： H05K7/20 , H01L25/00 , H05K7/02
CPC分类号： H01L25/0657 , G11C5/06 , H01L23/34 , H01L23/5384 , H01L23/64 , H01L24/17 , H01L2224/16 , H01L2224/1712 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2225/06589 , H01L2225/1058 , H01L2924/09701 , H01L2924/14 , H01L2924/1434 , H01L2924/19106 , H01L2924/00
摘要： A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.
摘要翻译：公开了一种叠层半导体器件及其制造方法。该装置包括具有相似图形的连接元件的上半导体器件和下半导体器件。当堆叠连接时，所得到的多个半导体器件包括穿过堆叠的串行连接路径，并且还可以包括并联连接路径，背面安装的大部件和垂直热导管。

5. 发明申请

US20080080285A1 Refresh circuit and refresh method in semiconductor memory device 有权
标题翻译：半导体存储器件中的刷新电路和刷新方法
公开(公告)号：US20080080285A1
公开(公告)日：2008-04-03
申请号：US11730275
申请日：2007-03-30
申请人： Jung Sunwoo , Yun-Sang Lee , Hoe-Ju Chung
发明人： Jung Sunwoo , Yun-Sang Lee , Hoe-Ju Chung
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40618
摘要： A refresh method for a semiconductor memory device having more than one bank group is provided. The refresh method may include applying an all-refresh command to one the bank groups, determining if one of the bank groups includes a bank undergoing a refresh operation when the all-refresh command is received, and performing an all-refresh operation based on the determination.
摘要翻译：提供了具有多于一个组组的半导体存储器件的刷新方法。刷新方法可以包括：将全刷新命令应用于银行组中的一个，当接收到全刷新命令时，确定银行组中的一个是否包括经历刷新操作的存储体，并且基于所述刷新操作执行全刷新操作决心。

6. 发明申请

US20060044912A1 Method and apparatus for refreshing memory device 审中-公开
标题翻译：用于刷新存储器件的方法和装置
公开(公告)号：US20060044912A1
公开(公告)日：2006-03-02
申请号：US11129073
申请日：2005-05-13
申请人： Byoung-Sul Kim , Yun-Sang Lee
发明人： Byoung-Sul Kim , Yun-Sang Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1042 , G11C11/406 , G11C11/40618
摘要： For refreshing a memory device, a refresh selection unit is enabled within a selected group of memory cells for refreshing at least one memory cell within the selected group in response to a refresh control signal and a refresh address signal from an external source. In addition, a normal operation circuit performs a normal operation on at least one memory cell of another group of memory cells while the at least one memory cell within the selected group is being refreshed to reduce refresh overhead.
摘要翻译：为了刷新存储器件，刷新选择单元在所选择的存储器单元组内启用，用于响应于来自外部源的刷新控制信号和刷新地址信号刷新所选组中的至少一个存储器单元。此外，正常操作电路对另一组存储器单元的至少一个存储单元执行正常操作，同时刷新所选组内的至少一个存储单元以减少刷新开销。

7. 发明授权

US06996754B1 Integrated circuit device having an internal state monitoring function 有权
标题翻译：具有内部状态监视功能的集成电路装置
公开(公告)号：US06996754B1
公开(公告)日：2006-02-07
申请号：US09672223
申请日：2000-09-27
申请人： Yun-Sang Lee
发明人： Yun-Sang Lee
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G11C29/1201
摘要： An integrated circuit device for testing is disclosed. The device includes a plurality of internal circuits for generating a plurality of internal signals, the internal signals used for addressing storage locations and for controlling internal operations, a first selection circuit for receiving the internal circuits in response to selection signals corresponding to test information signals, a second selection circuit for receiving output signals from the first selection circuit and output signals from a sense amplifier, and for opening an alternative one of transfer paths of the internal signals and the output signals in response to the selection signals, and a data output buffer for transferring output signals from the second selection signals to an outside of the device through data input/output pads.
摘要翻译：公开了一种用于测试的集成电路装置。该装置包括用于产生多个内部信号的多个内部电路，用于寻址存储位置和用于控制内部操作的内部信号，用于响应于与测试信息信号对应的选择信号接收内部电路的第一选择电路，第二选择电路，用于接收来自第一选择电路的输出信号和来自读出放大器的输出信号，以及响应于选择信号打开内部信号和输出信号的传输路径中的另一个传输路径;以及数据输出缓冲器用于通过数据输入/输出焊盘将输出信号从第二选择信号传送到设备的外部。

8. 发明授权

US06982917B2 DRAM partial refresh circuits and methods 有权
标题翻译： DRAM部分刷新电路和方法
公开(公告)号：US06982917B2
公开(公告)日：2006-01-03
申请号：US10192406
申请日：2002-07-10
申请人： Yun-sang Lee , Won-chang Jung
发明人： Yun-sang Lee , Won-chang Jung
IPC分类号： G11C7/00
CPC分类号： G11C11/406
摘要： Circuits and methods for refreshing memory banks in a DRAM are provided. A refresh circuit is provided in a DRAM having at least one memory bank and a plurality of word lines connected to memory locations in the memory bank. The word lines are subdivided into first and second groups of subword lines. The refresh circuit includes a delay circuit, a first driving circuit, and a second driving circuit. The delay circuit receives a refresh signal and outputs a delayed refresh signal a predetermined time delay later. The first driving circuit responds to the refresh signal by driving word lines in the first group of subword lines and the second driving circuit responds to the delayed refresh signal by driving word lines in the second group of subword lines.
摘要翻译：提供了用于刷新DRAM中的存储体的电路和方法。在具有至少一个存储体和连接到存储体中的存储器位置的多条字线的DRAM中提供刷新电路。字线被细分为第一和第二组子字线。刷新电路包括延迟电路，第一驱动电路和第二驱动电路。延迟电路接收刷新信号并且稍后在预定的时间延迟中输出延迟的刷新信号。第一驱动电路通过驱动第一组子字线中的字线来响应刷新信号，并且第二驱动电路通过驱动第二组子字线中的字线来响应延迟的刷新信号。

9. 发明申请

US20050243627A1 Semiconductor memory device with auto refresh to specified bank 有权
标题翻译：具有自动刷新到指定银行的半导体存储器件
公开(公告)号：US20050243627A1
公开(公告)日：2005-11-03
申请号：US11105169
申请日：2005-04-12
申请人： Yun-Sang Lee , Jung-Bae Lee
发明人： Yun-Sang Lee , Jung-Bae Lee
IPC分类号： G11C11/401 , G11C7/00 , G11C11/406
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/40618
摘要： Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. When all bank addresses have been supplied for the current row, the SDRAM circuit updates the current refresh row and repeats the process. This process can allow a memory controller to modify an auto-refresh bank sequence as necessary such that auto-refresh operations can proceed on some memory banks concurrently with reads and writes to other memory banks, allowing better utilization of the SDRAM circuit. Other embodiments are described and claimed.
摘要翻译：公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。当所有存储体地址已被提供给当前行时，SDRAM电路更新当前刷新行并重复该过程。该过程可以允许存储器控制器根据需要修改自动刷新存储体序列，使得自动刷新操作可以在一些存储体上与对其它存储体的读取和写入同时进行，从而更好地利用SDRAM电路。描述和要求保护其他实施例。

10. 发明授权

US06775170B2 Semiconductor memory device having write column select line or read column select line for shielding signal line 失效
标题翻译：具有用于屏蔽信号线的写列选择线或读列选择线的半导体存储器件
公开(公告)号：US06775170B2
公开(公告)日：2004-08-10
申请号：US10222110
申请日：2002-08-16
申请人： Yun-Sang Lee , Won-Chang Jung
发明人： Yun-Sang Lee , Won-Chang Jung
IPC分类号： G11C702
CPC分类号： G11C7/02 , G11C7/1048 , G11C2207/002
摘要： A semiconductor memory device comprises a write column select line or read column select line for shielding a signal line. The semiconductor memory device may include a signal line, a read column select line, and a write column select line. The signal line may transmit an operation signal related to the operation of the semiconductor memory device. The read column select line may transmit a read column select signal, which may control transfer of a data signal of a bit line to a data line. The write column select line may transmit a write column select signal, which may control transfer of the data signal of the data line to the bit line. One of the read column select line and the write column select line to transmit a deactivated column select signal among the read column select signal and the write column select signal, may be maintained at a predetermined logic level and may shield the signal line.
摘要翻译：半导体存储器件包括用于屏蔽信号线的写入列选择线或读取列选择线。半导体存储器件可以包括信号线，读取列选择线和写入列选择线。信号线可以发送与半导体存储器件的操作相关的操作信号。读列选择线可以发送读列选择信号，其可以控制位线的数据信号到数据线的传送。写列选择线可以发送写列选择信号，其可以控制数据线的数据信号到位线的传送。在读列选择信号和写列选择信号之间读取列选择线和写列选择线之一发送去激活的列选择信号可以保持在预定的逻辑电平并且可以屏蔽信号线。

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