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1. 发明申请

US20230137599A1 SURFACE TREATMENT OF SOI WAFER 有权
公开(公告)号：US20230137599A1
公开(公告)日：2023-05-04
申请号：US17586046
申请日：2022-01-27
申请人： Zing Semiconductor Corporation , Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
发明人： Xing WEI , Rongwang DAI , Ziwen WANG , Minghao LI , Hongtao XU , Meng CHEN
IPC分类号： H01L21/324 , C30B29/06 , H01L29/06
摘要： The present application provides a method of surface treatment of a SOI wafer comprising: providing a SOI wafer comprising a substrate, atop silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 Å; removing a native oxide layer from a surface of the top silicon layer by conducting a first isothermal annealing process at a first target temperature, wherein the first isothermal annealing process is under atmosphere of a mixture of argon and hydrogen; and planarizing the surface of the top silicon layer by conducting a second isothermal annealing process at a second target temperature, wherein the second target temperature is higher than the first target temperature, and the second isothermal annealing process is under atmosphere of argon. The present method can optimize the atmosphere for batch annealing to achieve better planarization than the conventional technologies. Specifically, the obtained top silicon layer of the SOI wafer has a surface roughness of less than 4 Å.

2. 发明申请

US20230133916A1 PROCESS OF SURFACE TREATMENT OF SOI WAFER 有权
公开(公告)号：US20230133916A1
公开(公告)日：2023-05-04
申请号：US17586254
申请日：2022-01-27
申请人： Zing Semiconductor Corporation , Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
发明人： Xing WEI , Rongwang DAI , Ziwen WANG , Minghao LI , Meng CHEN , Hongtao XU
IPC分类号： H01L21/762
摘要： The present application provides a process of surface treatment of a silicon-on-insulator (SOI) wafer comprising: providing a SOI wafer comprising a back substrate, a top silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 Å; conducting a first planarization to a surface of the top silicon layer by conducting a batch annealing process at a first target temperature, and conducting a second planarization to a surface of the top silicon layer by conducting a rapid thermal annealing process at a second target temperature. The present application combines the batch annealing process and the rapid thermal annealing process to optimize the SOI wafer, especially the surface roughness of the SOI wafer. The SOI wafer planarized by the two thermal annealing processes has a good surface roughness of the top silicon layer which satisfies process requirements.

3. 发明申请

US20230133092A1 SOI STRUCTURED SEMICONDUCTOR SILICON WAFER AND METHOD OF MAKING THE SAME 有权
公开(公告)号：US20230133092A1
公开(公告)日：2023-05-04
申请号：US17586324
申请日：2022-01-27
申请人： Zing Semiconductor Corporation , Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
发明人： Xing WEI , Rongwang DAI , Ziwen WANG , Minghao LI , Meng CHEN , Hongtao XU
IPC分类号： H01L21/324 , H01L21/762
摘要： A SOI structured semiconductor silicon wafer and a method of making the same is disclosed, comprising: loading a semiconductor silicon wafer in a first batch vertical furnace, and conducting a long-time thermal treatment; conducting a sacrificial oxidation process in a second batch vertical furnace after the long-time thermal treatment; conducting a rapid thermal annealing treatment after the second step ; wherein during the long-time thermal treatment, the semiconductor silicon wafer is kept in a protection atmosphere of pure , heated-up until meet a target temperature after changing the atmosphere of pure argon into a mixture gas of 1-n % Ar and n % H2, and then annealed in the atmosphere of a mixture of 1-n % Ar and n % hydrogen gas or pure Ar, and n is a value no greater than 10.

4. 发明授权

US11427925B2 Apparatus and method for ingot growth 有权
公开(公告)号：US11427925B2
公开(公告)日：2022-08-30
申请号：US16952564
申请日：2020-11-19
申请人： Zing Semiconductor Corporation
发明人： Xuliang Zhao
IPC分类号： C30B15/30 , C30B15/14 , C30B15/20 , C30B29/06
摘要： The present application provides an apparatus and a method for ingot growth. The apparatus for ingot growth comprises a growth furnace, a crucible, a heater, a lifting mechanism, an infrared detector, a dividing disc, a sensor and a control device. The crucible is located within the growth furnace. The lifting mechanism comprises a lifting wire and a driving device, wherein the lifting wire connects to the top of the ingot via one terminal and to the driving device via another terminal. The bottom of the ingot puts inside the crucible, and the ingot has plural crystal lines thereon. The infrared detector is located outside the growth furnace. The dividing disc is above the growth furnace, connects to the lifting mechanism, and rotates with the ingot synchronously under the driving of the lifting mechanism, and an orthographic projection of bisector of the dividing disc is between two adjacent crystal lines. The sensor is located on the periphery of the dividing disc. The control device connects to the infrared detector and the sensor in order to control the infrared detector to detect the ingot diameter while the sensor senses the bisector of the dividing disc. The present application is able to increase ingot quality and enhance product yield.

5. 发明申请

US20220181200A1 SILICON ON INSULATOR STRUCTURE AND METHOD OF MAKING THE SAME 有权
公开(公告)号：US20220181200A1
公开(公告)日：2022-06-09
申请号：US17191683
申请日：2021-03-03
申请人： Zing Semiconductor Corporation , SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
发明人： Xing WEI , Nan GAO , Zhongying XUE
IPC分类号： H01L21/762
摘要： The present invention provides a method of making a silicon on insulator (SOI) structure, comprising steps of: providing a bonded structure, the bonded structure comprises a first substrate, a second substrate and an insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a SOI structure; and processing the SOI structure with isothermal annealing technology at a pressure which is lower than atmospheric pressure.

6. 发明申请

US20220002903A1 HEAT SHIELD DEVICE FOR SINGLE CRYSTAL PRODUCTION FURNACE, CONTROL METHOD THEREOF AND SINGLE CRYSTAL PRODUCTION FURNACE 有权
公开(公告)号：US20220002903A1
公开(公告)日：2022-01-06
申请号：US17139990
申请日：2020-12-31
申请人： Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences , Zing Semiconductor Corporation
发明人： Zhongying Xue , Minghao Li , Xing Wei , Zhan Li , Tao Wei , Yun Liu
IPC分类号： C30B15/20 , C30B29/06 , C30B15/14
摘要： Disclosed a heat shield device for a single crystal production furnace. The heat shield device is disposed above a melt crucible of the single crystal production furnace, and comprises a shell, supporting members, heat insulation plates and a direction control component. The supporting members and the heat insulation plates are disposed within of the shell. One end of the supporting member is fixedly connected with an inner wall of the shell. The direction control component is connected with the heat insulation plate. The supporting members serve as supporting points of the heat insulation plates, and cooperate with the direction control component to control rotation of the heat insulation plates relative to the shell. A rotatable angle of the heat insulation plate faces a cylindrical surface of monocrystalline silicon, and a bottom surface of the shell faces interior of the melt crucible.

7. 发明申请

US20210071314A1 SEMICONDUCTOR CRYSTAL GROWTH APPARATUS 有权
公开(公告)号：US20210071314A1
公开(公告)日：2021-03-11
申请号：US17016446
申请日：2020-09-10
申请人： ZING SEMICONDUCTOR CORPORATION
发明人： Weimin Shen , Gang Wang
IPC分类号： C30B15/14 , C30B15/10 , C30B29/06
摘要： The present invention provides a crystal growth apparatus, including: a crucible configured to contain a melt for crystal growth; a heater disposed around the crucible and configured to heat the crucible; a heater deflector configured to surrounded the top and sides of the heater; an air vent, located on the heater deflector above the heater to let the air flow between the top space of the crystal growth apparatus and the surrounding space of the heater. According to the crystal growth device provided by the present invention, the air vent is provided on the heater deflector above the heater to connect the top space of the crystal growth device and the surrounding space of the heater, so that the heater is always in the atmosphere of the protective gas, the erosion of the heater surface by SiO vapor is avoided, the service life of the heater is extended, and the stability of the crystal growth quality is improved.

8. 发明申请

US20210010155A1 SEMICONDUCTOR CRYSTAL GROWTH APPARATUS 有权
公开(公告)号：US20210010155A1
公开(公告)日：2021-01-14
申请号：US16904563
申请日：2020-06-18
申请人： Zing Semiconductor Corporation
发明人： Weimin Shen , Gang Wang , Xianliang Deng , Hanyi Huang , Wee Teck Tan
IPC分类号： C30B15/30 , C30B29/06
摘要： The present invention provides a semiconductor crystal growth apparatus, which comprises a furnace body, a crucible, a pulling device, a deflector, and a magnetic field applying device. The crucible is disposed inside the furnace body for containing silicon melt. The pulling device is disposed on the top of the furnace body for pulling a silicon ingot from the silicon melt. The deflector is in a barrel shape and is disposed in the furnace body in a vertical direction, and the pulling device pulls the silicon ingot in a vertical direction and through the deflector. The magnetic field applying device is configured to apply a magnetic field to the silicon melt in the crucible, in which the distance between the bottom of the deflector and the liquid level of the silicon melt in the direction of the magnetic field is less than that between the bottom of the deflector and the silicon melt in the direction perpendicular to the direction of the magnetic field.

9. 发明授权

US10170356B2 SOI substrate and manufacturing method thereof 有权
公开(公告)号：US10170356B2
公开(公告)日：2019-01-01
申请号：US15198805
申请日：2016-06-30
申请人： ZING SEMICONDUCTOR CORPORATION
发明人： Deyuan Xiao , Richard R. Chang
IPC分类号： H01L21/762 , H01L21/02 , H01L29/34
摘要： This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer at a deuterium atmosphere; separating a part of the first wafer from the second wafer; and forming a deuterium doped layer on the second wafer.

10. 发明授权

US09972637B2 Metal-ono-vacuum tube charge trap flash (VTCTF) nonvolatile memory and the method for making the same 有权
公开(公告)号：US09972637B2
公开(公告)日：2018-05-15
申请号：US15783115
申请日：2017-10-13
申请人： ZING SEMICONDUCTOR CORPORATION
发明人： Deyuan Xiao
IPC分类号： H01L29/66 , H01L21/28 , H01L21/324 , H01L27/11568 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L21/324 , H01L27/1157 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： The present invention relates to a method for preparing vacuum tube flash memory structure, to form a vacuum channel in the flash memory, and using oxide-nitride-oxide (ONO) composite materials as gate dielectric layer, wherein the nitride layer serves as a charge-trap layer to provide a blocking insulating between the gate electrode and the vacuum channel. The present structure exhibits superior program and erase speed as well as the retention time. It also provide with excellent gate controllability and negligible gate leakage current due to adoption ONO as the gate dielectric layer.

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