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1. 发明申请

US20210173783A1 INSTRUCTION CACHE PREFETCH THROTTLE 有权
公开(公告)号：US20210173783A1
公开(公告)日：2021-06-10
申请号：US16709831
申请日：2019-12-10
申请人： Advanced Micro Devices, Inc.
发明人： Aparna Thyagarajan , Ashok Tirupathy Venkatachar , Marius Evers , Angelo Wong , William E. Jones
IPC分类号： G06F12/0862
摘要： Techniques for controlling prefetching of instructions into an instruction cache are provided. The techniques include tracking either or both of branch target buffer misses and instruction cache misses, modifying a throttle toggle based on the tracking, and adjusting prefetch activity based on the throttle toggle.

2. 发明授权

US10929141B1 Selective use of taint protection during speculative execution 有权
公开(公告)号：US10929141B1
公开(公告)日：2021-02-23
申请号：US16293266
申请日：2019-03-05
申请人： ADVANCED MICRO DEVICES, INC.
发明人： David Kaplan , Marius Evers
IPC分类号： G06F9/38 , G06F9/30
摘要： A state of a first architectural register in a processing system is changed from a first state to a second state that indicates that the first architectural register is to be monitored during speculative execution. A second architectural register in the processing system is associated with a third state in response to the first architectural register being a source register for a memory load instruction that loads data from a memory into the second architectural register during speculative execution. Use of data in the second architectural register is constrained during speculative operations while the second architectural register is in the third state. In some cases, a “set taint” instruction is executed to change the state of the first architectural register from the first state to the second state.

3. 发明申请

US20200272463A1 PROCESSOR WITH ACCELERATED LOCK INSTRUCTION OPERATION 审中-公开
公开(公告)号：US20200272463A1
公开(公告)日：2020-08-27
申请号：US16286702
申请日：2019-02-27
申请人： Advanced Micro Devices, Inc.
发明人： Scott Thomas Bingham , Marius Evers , Krishnan V. Ramani , Thomas Kunjan
IPC分类号： G06F9/30 , G06F12/0875
摘要： A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.

4. 发明申请

US20190391813A1 LOW LATENCY SYNCHRONIZATION FOR OPERATION CACHE AND INSTRUCTION CACHE FETCHING AND DECODING INSTRUCTIONS 审中-公开
公开(公告)号：US20190391813A1
公开(公告)日：2019-12-26
申请号：US16014715
申请日：2018-06-21
申请人： Advanced Micro Devices, Inc.
发明人： Marius Evers , Dhanaraj Bapurao Tavare , Ashok Tirupathy Venkatachar , Arunachalam Annamalai , Donald A. Priore , Douglas R. Williams
IPC分类号： G06F9/38
摘要： The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.

5. 发明申请

US20150026414A1 STRIDE PREFETCHING ACROSS MEMORY PAGES 审中-公开
标题翻译：横向记录页面
公开(公告)号：US20150026414A1
公开(公告)日：2015-01-22
申请号：US13944148
申请日：2013-07-17
申请人： Advanced Micro Devices, Inc.
发明人： John Kalamatianos , Paul Keltcher , Marius Evers , Chitresh Narasimhaiah
IPC分类号： G06F12/08
摘要： A prefetcher maintains the state of stored prefetch information, such as a prefetch confidence level, when a prefetch would cross a memory page boundary. The maintained prefetch information can be used both to identify whether the stride pattern for a particular sequence of demand requests persists after the memory page boundary has been crossed, and to continue to issue prefetch requests according to the identified pattern. The prefetcher therefore does not have re-identify a stride pattern each time a page boundary is crossed by a sequence of demand requests, thereby improving the efficiency and accuracy of the prefetcher.
摘要翻译：当预取将跨越内存页边界时，预取器维护存储的预取信息的状态，例如预取置信水平。可以使用维护的预取信息来识别在存储器页边界已经被越过之后特定的请求请求序列的步幅模式是否持续，并且根据所识别的模式继续发出预取请求。因此，每次通过一系列请求请求来划分页边界时，预取器不会重新识别步幅，从而提高预取器的效率和准确性。

6. 发明申请

US20140108740A1 PREFETCH THROTTLING 审中-公开
标题翻译：预制曲折
公开(公告)号：US20140108740A1
公开(公告)日：2014-04-17
申请号：US13653951
申请日：2012-10-17
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Todd Rafacz , Marius Evers , Chitresh Narasimhaiah
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： A processing system monitors memory bandwidth available to transfer data from memory to a cache. In addition, the processing system monitors a prefetching accuracy for prefetched data. If the amount of available memory bandwidth is low and the prefetching accuracy is also low, prefetching can be throttled by reducing the amount of data prefetched. The prefetching can be throttled by changing the frequency of prefetching, prefetching depth, prefetching confidence levels, and the like.
摘要翻译：处理系统监视可用于将数据从存储器传输到高速缓存的存储器带宽。此外，处理系统监视预取数据的预取精度。如果可用存储器带宽的数量低，并且预取精度也很低，则可以通过减少预取数据量来限制预取。可以通过改变预取的频率，预取深度，预取置信水平等来限制预取。

7. 发明授权

US10949201B2 Processor with accelerated lock instruction operation 有权
公开(公告)号：US10949201B2
公开(公告)日：2021-03-16
申请号：US16286702
申请日：2019-02-27
申请人： Advanced Micro Devices, Inc.
发明人： Scott Thomas Bingham , Marius Evers , Krishnan V. Ramani , Thomas Kunjan
IPC分类号： G06F9/30 , G06F12/0875 , G06F12/0815
摘要： A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.

8. 发明授权

US10915322B2 Using loop exit prediction to accelerate or suppress loop mode of a processor 有权
公开(公告)号：US10915322B2
公开(公告)日：2021-02-09
申请号：US16134440
申请日：2018-09-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Arunachalam Annamalai , Marius Evers , Aparna Thyagarajan , Anthony Jarvis
IPC分类号： G06F9/30 , G06F9/38 , G06F1/3296
摘要： A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.

9. 发明申请

US20190310845A1 TRACKING STORES AND LOADS BY BYPASSING LOAD STORE UNITS 审中-公开
公开(公告)号：US20190310845A1
公开(公告)日：2019-10-10
申请号：US16450897
申请日：2019-06-24
申请人： Advanced Micro Devices, Inc.
发明人： Krishnan V. Ramani , Kai Troester , Frank C. Galloway , David N. Suggs , Michael D. Achenbach , Betty Ann McDaniel , Marius Evers
IPC分类号： G06F9/28 , G06F9/30
摘要： A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. Store-load pairs which have a strong history of store-to-load forwarding are identified. Once identified, the load is memory renamed to the register stored by the store. The memory dependency predictor may also be used to detect loads that are dependent on a store but cannot be renamed. In such a configuration, the dependence is signaled to the load store unit and the load store unit uses the information to issue the load after the identified store has its physical address.

10. 发明授权

US09529720B2 Variable distance bypass between tag array and data array pipelines in a cache 有权
标题翻译：缓存中标签阵列与数据阵列管道之间的可变距离旁路
公开(公告)号：US09529720B2
公开(公告)日：2016-12-27
申请号：US13912809
申请日：2013-06-07
申请人： Advanced Micro Devices, Inc.
发明人： Marius Evers , John Kalamatianos , Carl D. Dietz , Richard E. Klass , Ravindra N. Bhargava
IPC分类号： G06F12/08
CPC分类号： G06F12/0855 , G06F12/0844 , G06F12/0846
摘要： The present application describes embodiments of techniques for picking a data array lookup request for execution in a data array pipeline a variable number of cycles behind a corresponding tag array lookup request that is concurrently executing in a tag array pipeline. Some embodiments of a method for picking the data array lookup request include picking the data array lookup request for execution in a data array pipeline of a cache concurrently with execution of a tag array lookup request in a tag array pipeline of the cache. The data array lookup request is picked for execution in response to resources of the data array pipeline becoming available after picking the tag array lookup request for execution. Some embodiments of the method may be implemented in a cache.
摘要翻译：本申请描述了用于在数据阵列流水线中选择用于执行数据阵列查找请求的技术的实施例，该数据阵列查找请求在标签阵列管线中同时执行的对应的标签数组查找请求后面的可变数量的循环。用于选择数据阵列查找请求的方法的一些实施例包括在高速缓存的标签阵列管线中执行标签阵列查找请求的同时，在高速缓存的数据阵列流水线中选择用于执行的数据阵列查找请求。选择数据数组查找请求以在执行标签数组查找请求之后响应于数据数组流水线变得可用的资源进行执行。该方法的一些实施例可以在高速缓存中实现。

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