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1. 发明授权

US07944452B1 Methods and systems for reusing memory addresses in a graphics system 有权
标题翻译：在图形系统中重复使用存储器地址的方法和系统
公开(公告)号：US07944452B1
公开(公告)日：2011-05-17
申请号：US11552093
申请日：2006-10-23
申请人： Adam Clark Wietkemper , Steven E. Molnar , Mark J. French , Cass W. Everitt
发明人： Adam Clark Wietkemper , Steven E. Molnar , Mark J. French , Cass W. Everitt
IPC分类号： G06F12/02 , G06F12/10 , G06F12/06
CPC分类号： G06F12/10 , G06F12/0223 , G09G5/39
摘要： Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint in screen space to a group of contiguous physical memory locations in a memory system, determining a first physical memory address for a first transaction associated with the footprint, wherein the first physical memory address is within the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits associated with the second transaction, and combining a portion of the first physical memory address with the set of least significant bits associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.
摘要翻译：公开了用于重新使用图形系统中的存储器地址的方法和系统，从而可以减少地址转换硬件的实例。本发明的一个实施例提出了一种方法，其包括将屏幕空间中的占位面积映射到存储器系统中的一组连续的物理存储器位置，确定与所述覆盖区相关联的第一事务的第一物理存储器地址，其中所述第一物理存储器地址在连续的物理存储器位置组内，确定也与占用空间相关联的第二事务，确定与第二事务相关联的一组最低有效位，以及将第一物理存储器地址的一部分与与第二事务相关联的一组最低有效位以产生用于第二事务的第二物理存储器地址，从而避免第二完整地址转换。

2. 发明授权

US07626588B1 Prescient cache management 有权
标题翻译：预备缓存管理
公开(公告)号：US07626588B1
公开(公告)日：2009-12-01
申请号：US11454225
申请日：2006-06-16
申请人： Steven E. Molnar , Mark J. French , Cass W. Everitt , Adam Clark Weitkemper , Phillip Keslin , David L. Anderson , George R. Lynch
发明人： Steven E. Molnar , Mark J. French , Cass W. Everitt , Adam Clark Weitkemper , Phillip Keslin , David L. Anderson , George R. Lynch
IPC分类号： G09G5/36 , G06F12/00
CPC分类号： G06F12/0802 , G06T1/60 , G06T11/40 , G09G2360/121
摘要： Prescient cache management methods and systems are disclosed. In one embodiment, a local cache that operates within a raster engine operations stage of a graphics rendering pipeline is managed by following a number of caching decisions related to a number of cached tiles. Each of these cached tiles has a certain priority to remain in the local cache, with the priority corresponding to a conflict type received from a buffer operating within a pre-raster engine operations stage of the graphics rendering pipeline.
摘要翻译：公开了高级缓存管理方法和系统。在一个实施例中，在图形渲染流水线的光栅引擎操作阶段内操作的本地高速缓存通过跟随与多个缓存的瓦片相关的多个缓存判定来管理。这些缓存的瓦片中的每一个具有保留在本地高速缓存中的一定优先级，其优先级对应于从在图形呈现流水线的前光栅引擎操作阶段内操作的缓冲器接收到的冲突类型。

3. 发明授权

US07616209B1 Prescient cache management 有权
标题翻译：预备缓存管理
公开(公告)号：US07616209B1
公开(公告)日：2009-11-10
申请号：US11454230
申请日：2006-06-16
申请人： Steven E. Molnar , Mark J. French , Cass W. Everitt , Adam Clark Weitkemper , Phillip Keslin , David L. Anderson , George R. Lynch
发明人： Steven E. Molnar , Mark J. French , Cass W. Everitt , Adam Clark Weitkemper , Phillip Keslin , David L. Anderson , George R. Lynch
IPC分类号： G09G5/36 , G06F13/00 , G06F13/28
CPC分类号： G09G5/363 , G06T1/60 , G06T11/40 , G09G5/39 , G09G2360/121 , G09G2360/122
摘要： Prescient cache management methods and systems are disclosed. In one embodiment, within a pre-raster engine operations stage in a graphics rendering pipeline, tile entries are stored in a buffer. Each of these tile entries is related a transaction request that enters the pre-raster engine operations stage and has a screen coordinates field and a conflict field. If this buffer includes a first tile entry, which is related to a first transaction request associated with a first tile, and a second tile entry, which is related to a second transaction request that enters the pre-raster engine operations stage after the first transaction request and is also associated with the first tile, the conflict field of the first tile entry is updated with a conflict type that reflects a number of tile entries between the first tile entry and the second tile entry.
摘要翻译：公开了高级缓存管理方法和系统。在一个实施例中，在图形渲染流水线的光栅前引擎操作阶段内，瓦片条目被存储在缓冲器中。这些瓦片条目中的每一个都与进入光栅前引擎操作阶段并具有屏幕坐标字段和冲突字段的事务请求相关联。如果该缓冲器包括第一瓦片条目，其与与第一瓦片相关联的第一事务请求和第二瓦片条目相关，第二瓦片条目与在第一交易之后进入前光栅引擎操作阶段的第二事务请求相关请求并且还与第一瓦片相关联，用反映第一瓦片条目和第二瓦片条目之间的多个瓦片条目的冲突类型来更新第一瓦片条目的冲突字段。

4. 发明授权

US07519797B1 Hierarchical multi-precision pipeline counters 有权
标题翻译：分层多精度管道计数器
公开(公告)号：US07519797B1
公开(公告)日：2009-04-14
申请号：US11556020
申请日：2006-11-02
申请人： Gregory J. Stiehl , David L. Anderson , Cass W. Everitt , Mark J. French , Steven E. Molnar
发明人： Gregory J. Stiehl , David L. Anderson , Cass W. Everitt , Mark J. French , Steven E. Molnar
IPC分类号： G06F9/00 , G06F15/76
CPC分类号： G06F9/3867 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： An event occurring in a graphics pipeline is detected and counted at the location of its occurrence using an event detector and a local counter. The event count maintained by the local counter is reported asynchronously to a global counter. The global counter is configured to be of higher precision than the local counter and is positioned at a place that is convenient for reporting the events, e.g., at the end of the graphics pipeline.
摘要翻译：使用事件检测器和本地计数器在其出现的位置处检测并计数在图形管线中发生的事件。本地计数器维护的事件计数器与全局计数器异步报告。全局计数器被配置为比本地计数器具有更高的精度，并且位于便于报告事件的位置，例如在图形流水线的末端。

5. 发明授权

US08085272B1 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08085272B1
公开(公告)日：2011-12-27
申请号：US11556657
申请日：2006-11-03
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
IPC分类号： G06F15/80
CPC分类号： G06T15/005
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated with the common input stream, generating a plurality of fragment streams from the common input stream, inserting a marker based on an occurrence of the periodic event in a first fragment stream in the multiple fragment streams, and utilizing the marker to influence the processing of the first fragment stream so that a plurality of raster operation (ROP) request streams maintains substantially the same coherence as the common input stream. Each fragment stream is independently processed and corresponds to one of the ROP request streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种方法，其包括以下步骤：接收公共输入流，跟踪与公共输入流相关联的周期性事件，从公共输入流生成多个片段流，插入标记基于所述多个片段流中的第一片段流中的所述周期性事件的发生，并且利用所述标记来影响所述第一片段流的处理，使得多个光栅操作（ROP）请求流保持基本相同的一致性公共输入流。每个片段流被独立地处理并对应于其中一个ROP请求流。

6. 发明授权

US07999820B1 Methods and systems for reusing memory addresses in a graphics system 有权
标题翻译：在图形系统中重复使用存储器地址的方法和系统
公开(公告)号：US07999820B1
公开(公告)日：2011-08-16
申请号：US11953812
申请日：2007-12-10
申请人： Adam Clark Weitkemper , Steven E. Molnar , Mark J. French , Cass W. Everitt
发明人： Adam Clark Weitkemper , Steven E. Molnar , Mark J. French , Cass W. Everitt
IPC分类号： G06F12/02 , G06F12/10 , G06F12/06
CPC分类号： G06F12/0223 , G06F12/10 , G09G5/39 , G09G2360/122
摘要： Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint on a display screen to a group of contiguous physical memory locations in a memory system, determining an anchor physical memory address from a first transaction associated with the footprint, wherein the anchor physical memory address corresponds to an anchor in the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits (LSBs) associated with the second transaction, and combining the anchor physical memory address with the set of LSBs associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.
摘要翻译：公开了用于重新使用图形系统中的存储器地址的方法和系统，从而可以减少地址转换硬件的实例。本发明的一个实施例提出了一种方法，其包括将显示屏幕上的占位面积映射到存储器系统中的一组连续物理存储器位置，从与所述覆盖区相关联的第一事务确定锚物理存储器地址，其中，锚物理存储器地址对应于连续物理存储器位置组中的锚点，确定也与占用空间相关联的第二事务，确定与第二事务相关联的一组最低有效位（LSB），以及组合锚物理存储器地址与与第二事务相关联的一组LSB产生用于第二事务的第二物理存储器地址，从而避免第二次完全地址转换。

7. 发明授权

US08139069B1 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08139069B1
公开(公告)日：2012-03-20
申请号：US11556660
申请日：2006-11-03
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
IPC分类号： G06F15/80
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。

8. 发明授权

US08862823B1 Compression status caching 有权
标题翻译：压缩状态缓存
公开(公告)号：US08862823B1
公开(公告)日：2014-10-14
申请号：US12340503
申请日：2008-12-19
申请人： David B. Glasco , Cass W. Everitt , David Kirk Mcallister , Emmett M. Kilgariff , George R. Lynch , James Roberts , Karan Mehra , Patrick R. Marchand , Peter B. Holmqvist , Steven E. Molnar
发明人： David B. Glasco , Cass W. Everitt , David Kirk Mcallister , Emmett M. Kilgariff , George R. Lynch , James Roberts , Karan Mehra , Patrick R. Marchand , Peter B. Holmqvist , Steven E. Molnar
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0897 , G06F12/0848 , G06F12/1009 , G06F12/123 , G06F2212/1041 , G06F2212/401 , G06F2212/455 , G06F2212/466 , G06T1/60
摘要： One embodiment of the present invention sets forth a compression status cache configured to store compression information for blocks of memory stored within an external memory. A data cache unit is configured to request, in response to a cache miss, compressed data from the external memory based on compression information stored in the compression status bit cache. The compression status for active buffers is dynamically swapped into the compression status cache as needed. Different compression formats may be specified for one or more tiles within an active buffer. One advantage of the disclosed compression status cache is that a lame amount of attached memory may be allocated as compressible memory blocks, without incurring a corresponding die area cost because a portion of the compression status stored off chip in attached memory is cached in the compression status cache.
摘要翻译：本发明的一个实施例提出了一种被配置为存储存储在外部存储器中的存储器块的压缩信息的压缩状态缓存。数据高速缓存单元被配置为基于存储在压缩状态位高速缓存中的压缩信息，响应于高速缓存未命中来请求来自外部存储器的压缩数据。活动缓冲区的压缩状态根据需要动态交换到压缩状态缓存。可以为活动缓冲区内的一个或多个瓦片指定不同的压缩格式。所公开的压缩状态高速缓存的一个优点是可以将大量附加存储器分配为可压缩存储器块，而不会引起相应的管芯区域成本，因为存储在附加存储器中的芯片外的存储器的一部分被缓存在压缩状态缓存。

9. 发明授权

US08379033B2 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08379033B2
公开(公告)日：2013-02-19
申请号：US13399458
申请日：2012-02-17
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
IPC分类号： G06F15/80
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。

10. 发明申请

US20100001999A1 Hybrid Multisample/Supersample Antialiasing 有权
标题翻译：混合多采样/超采样抗锯齿
公开(公告)号：US20100001999A1
公开(公告)日：2010-01-07
申请号：US12167997
申请日：2008-07-03
申请人： Cass W. Everitt , Steven E. Molnar
发明人： Cass W. Everitt , Steven E. Molnar
IPC分类号： G06T15/50 , G06T1/20 , G09G5/00
CPC分类号： G06T11/40
摘要： A system and method for dynamically adjusting the pixel sampling rate during primitive shading can improve image quality or increase shading performance. Hybrid antialiasing is performed by selecting a number of shaded samples per pixel fragment. A combination of supersample and multisample antialiasing is used where a cluster of sub-pixel samples (multisamples) is processed for each pass through a fragment shader pipeline. The number of shader passes and multisamples in each cluster can be determined dynamically for each primitive based on rendering state.
摘要翻译：在原始着色中动态调整像素采样率的系统和方法可以提高图像质量或增加遮蔽性能。通过选择每个像素片段的阴影样本数来执行混合抗混叠。使用超采样和多采样抗锯齿的组合，其中对于通过片段着色器管线的每次通过处理子像素采样（多采样）的簇。可以基于呈现状态为每个基元动态地确定每个集群中的着色器遍数和多个样本的数量。

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