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1. 发明授权

US08316017B2 Apparatus and method for the detection of and recovery from inappropriate bus access in microcontroller circuits 有权
标题翻译：用于在微控制器电路中检测和恢复从不正确的总线访问的装置和方法
公开(公告)号：US08316017B2
公开(公告)日：2012-11-20
申请号：US11426528
申请日：2006-06-26
申请人： Alain Vergnes , Renaud Tiennot
发明人： Alain Vergnes , Renaud Tiennot
IPC分类号： G06F7/00 , G06F17/30 , G06F7/04 , G06F11/00
CPC分类号： G06F21/71
摘要： An inappropriate-access module is incorporated in a computer system along with other computer system modules. The inappropriate-access module is connected to a read address decoder and controlling logic located within various other modules. The inappropriate-access module detects inappropriate read accesses or the occurrence of the inappropriate access during operations performed on related sensitive system resources in accompanying computer system modules. The inappropriate-access module produces an inappropriate-access flag, made available to the rest of the system, which invokes responses in the accompanying modules such as a halt in processing and protective measures for system resources. Additionally, a related logic block is able to detect the inappropriate access and produce an inappropriate-access trigger which causes a halt to processing within the logic block as well as in related system modules.
摘要翻译：不合适的访问模块与其他计算机系统模块一起并入计算机系统中。不正当访问模块连接到读地址解码器和位于各种其他模块内的控制逻辑。不适当的访问模块在随附的计算机系统模块中对相关敏感系统资源执行的操作期间检测不适当的读取访问或发生不适当的访问。不适当的访问模块产生不适当的访问标志，对系统的其余部分可用，其调用所附模块中的响应，例如处理中的停止和用于系统资源的保护措施。另外，相关的逻辑块能够检测不适当的访问并产生不合适的访问触发器，这导致停止在逻辑块内以及在相关系统模块中的处理。

2. 发明授权

US08601197B2 Microcontroller including flexible connections between modules 有权
标题翻译：微控制器包括模块之间的灵活连接
公开(公告)号：US08601197B2
公开(公告)日：2013-12-03
申请号：US12946699
申请日：2010-11-15
申请人： Alain Vergnes , Renaud Tiennot , Guillaume Pean
发明人： Alain Vergnes , Renaud Tiennot , Guillaume Pean
IPC分类号： G06F13/36
CPC分类号： G06F13/4022
摘要： A microcontroller includes a system bus matrix to connect various modules. The microcontroller also includes direct connections between modules. For example, the microcontroller may include a direct connection between a data processing module and a memory controller module to improve the transfer rate for data that is processed by the data processing module.
摘要翻译：微控制器包括用于连接各种模块的系统总线矩阵。微控制器还包括模块之间的直接连接。例如，微控制器可以包括数据处理模块和存储器控制器模块之间的直接连接，以提高由数据处理模块处理的数据的传输速率。

3. 发明申请

US20100241874A1 Method and Apparatus to Scramble Data Stored in Memories Accessed by Microprocessors 有权
标题翻译：用于加密存储在微处理器访问的存储器中的数据的方法和装置
公开(公告)号：US20100241874A1
公开(公告)日：2010-09-23
申请号：US12406817
申请日：2009-03-18
申请人： Alain Vergnes , Renaud Tiennot
发明人： Alain Vergnes , Renaud Tiennot
IPC分类号： H04L9/06
CPC分类号： G06F21/71
摘要： A scrambler/descrambler module included in an integrated circuit device is operable for receiving a scrambling key and constant data that is unique to the integrated circuit device. The scrambler/descrambler module includes a first layer or circuit arrangement that uses a scrambling key to generate first scrambled data. The scrambler/descrambler module includes a second layer or second circuit arrangement that uses data that is unique to the integrated circuit device, and that is constant over the life of the integrated circuit device, to scramble the first scrambled data to generate second scrambled data.
摘要翻译：包括在集成电路装置中的扰码器/解扰器模块可操作用于接收加扰密钥和集成电路设备唯一的恒定数据。加扰器/解扰器模块包括使用加扰密钥生成第一加扰数据的第一层或电路装置。加扰器/解扰器模块包括使用集成电路器件唯一的数据并且在集成电路器件的整个使用寿命期间恒定的第二层或第二电路装置，以加扰第一加扰数据以产生第二加扰数据。

4. 发明申请

US20120124261A1 MICROCONTROLLER INCLUDING FLEXIBLE CONNECTIONS BETWEEN MODULES 有权
标题翻译：微控制器，包括模块之间的灵活连接
公开(公告)号：US20120124261A1
公开(公告)日：2012-05-17
申请号：US12946699
申请日：2010-11-15
申请人： Alain Vergnes , Renaud Tiennot , Guillaume Pean
发明人： Alain Vergnes , Renaud Tiennot , Guillaume Pean
IPC分类号： G06F13/36 , G06F13/14 , G06F13/00
CPC分类号： G06F13/4022
摘要： A microcontroller includes a system bus matrix to connect various modules. The microcontroller also includes direct connections between modules. For example, the microcontroller may include a direct connection between a data processing module and a memory controller module to improve the transfer rate for data that is processed by the data processing module.
摘要翻译：微控制器包括用于连接各种模块的系统总线矩阵。微控制器还包括模块之间的直接连接。例如，微控制器可以包括数据处理模块和存储器控制器模块之间的直接连接，以提高由数据处理模块处理的数据的传输速率。

5. 发明申请

US20100262880A1 QUADRATURE DECODER FILTERING CIRCUITRY FOR MOTOR CONTROL 有权
标题翻译：用于电动机控制的四路解码器滤波电路
公开(公告)号：US20100262880A1
公开(公告)日：2010-10-14
申请号：US12421348
申请日：2009-04-09
申请人： Alain Vergnes , Renaud Tiennot
发明人： Alain Vergnes , Renaud Tiennot
IPC分类号： H03M13/00 , G06F11/07
CPC分类号： H02P31/00
摘要： The disclosed quadrature decoder filtering circuitry for motor control uses one quadrature signal to correct an error in the other quadrature signal, thus allowing a noisy signal due to large dust particles or scratches to be recovered. In some implementations, a system processing for quadrature signals comprises a first circuitry triggered by edges of a first quadrature signal to detect inactivity of a second quadrature signal during consecutive edges of the first quadrature signal. A second circuitry is operable to count the number of consecutive edges of the first quadrature signal during inactivity of the second quadrature signal. A third circuitry is operable to combine transitions of the first quadrature signal with the second quadrature signal during a period of time determined by the count value of the second circuitry.
摘要翻译：所公开的用于电动机控制的正交解码器滤波电路使用一个正交信号来校正另一个正交信号中的误差，从而允许由于大的灰尘颗粒或划痕而产生的噪声信号被恢复。在一些实现中，用于正交信号的系统处理包括由第一正交信号的边缘触发的第一电路，以在第一正交信号的连续边缘期间检测第二正交信号的不活动。第二电路可操作以在第二正交信号的不活动期间对第一正交信号的连续边缘的数量进行计数。第三电路可操作以在由第二电路的计数值确定的时间段期间组合第一正交信号的转换与第二正交信号。

6. 发明授权

US08190956B2 Quadrature decoder filtering circuitry for motor control 有权
标题翻译：用于电机控制的正交译码器滤波电路
公开(公告)号：US08190956B2
公开(公告)日：2012-05-29
申请号：US12421348
申请日：2009-04-09
申请人： Alain Vergnes , Renaud Tiennot
发明人： Alain Vergnes , Renaud Tiennot
IPC分类号： G06F11/00
CPC分类号： H02P31/00
摘要： The disclosed quadrature decoder filtering circuitry for motor control uses one quadrature signal to correct an error in the other quadrature signal, thus allowing a noisy signal due to large dust particles or scratches to be recovered. In some implementations, a system processing for quadrature signals comprises a first circuitry triggered by edges of a first quadrature signal to detect inactivity of a second quadrature signal during consecutive edges of the first quadrature signal. A second circuitry is operable to count the number of consecutive edges of the first quadrature signal during inactivity of the second quadrature signal. A third circuitry is operable to combine transitions of the first quadrature signal with the second quadrature signal during a period of time determined by the count value of the second circuitry.
摘要翻译：所公开的用于电动机控制的正交解码器滤波电路使用一个正交信号来校正另一个正交信号中的误差，从而允许由于大的灰尘颗粒或划痕而产生的噪声信号被恢复。在一些实现中，用于正交信号的系统处理包括由第一正交信号的边缘触发的第一电路，以在第一正交信号的连续边缘期间检测第二正交信号的不活动。第二电路可操作以在第二正交信号的不活动期间对第一正交信号的连续边缘的数量进行计数。第三电路可操作以在由第二电路的计数值确定的时间段期间组合第一正交信号的转换与第二正交信号。

7. 发明授权

US08745410B2 Method and apparatus to scramble data stored in memories accessed by microprocessors 有权
标题翻译：对存储在由微处理器访问的存储器中的数据进行加扰的方法和装置
公开(公告)号：US08745410B2
公开(公告)日：2014-06-03
申请号：US12406817
申请日：2009-03-18
申请人： Alain Vergnes , Renaud Tiennot
发明人： Alain Vergnes , Renaud Tiennot
IPC分类号： H04L29/06
CPC分类号： G06F21/71
摘要： A scrambler/descrambler module included in an integrated circuit device is operable for receiving a scrambling key and constant data that is unique to the integrated circuit device. The scrambler/descrambler module includes a first layer or circuit arrangement that uses a scrambling key to generate first scrambled data. The scrambler/descrambler module includes a second layer or second circuit arrangement that uses data that is unique to the integrated circuit device, and that is constant over the life of the integrated circuit device, to scramble the first scrambled data to generate second scrambled data.
摘要翻译：包括在集成电路装置中的扰码器/解扰器模块可操作用于接收加扰密钥和集成电路设备唯一的恒定数据。加扰器/解扰器模块包括使用加扰密钥生成第一加扰数据的第一层或电路装置。加扰器/解扰器模块包括使用集成电路器件唯一的且在集成电路器件的整个使用寿命期间恒定的数据的第二层或第二电路装置，以加扰第一加扰数据以产生第二加扰数据。

8. 发明申请

US20070233429A1 APPARATUS AND METHOD FOR THE DETECTION OF AND RECOVERY FROM INAPPROPRIATE BUS ACCESS IN MICROCONTROLLER CIRCUITS 有权
标题翻译：微处理器电路中不准确的总线接入检测和恢复的装置和方法
公开(公告)号：US20070233429A1
公开(公告)日：2007-10-04
申请号：US11426528
申请日：2006-06-26
申请人： Alain Vergnes , Renaud Tiennot
发明人： Alain Vergnes , Renaud Tiennot
IPC分类号： G06F19/00 , G06F17/40
CPC分类号： G06F21/71
摘要： An inappropriate-access module is incorporated in a computer system along with other computer system modules. The inappropriate-access module is connected to a read address decoder and controlling logic located within various other modules. The inappropriate-access module detects inappropriate read accesses or the occurrence of the inappropriate access during operations performed on related sensitive system resources in accompanying computer system modules. The inappropriate-access module produces an inappropriate-access flag, made available to the rest of the system, which invokes responses in the accompanying modules such as a halt in processing and protective measures for system resources. Additionally, a related logic block is able to detect the inappropriate access and produce an inappropriate-access trigger which causes a halt to processing within the logic block as well as in related system modules.
摘要翻译：不合适的访问模块与其他计算机系统模块一起并入计算机系统中。不正当访问模块连接到读地址解码器和位于各种其他模块内的控制逻辑。不适当的访问模块在随附的计算机系统模块中对相关敏感系统资源执行的操作期间检测不适当的读取访问或发生不适当的访问。不适当的访问模块产生不适当的访问标志，对系统的其余部分可用，其调用所附模块中的响应，例如处理中的停止和用于系统资源的保护措施。另外，相关的逻辑块能够检测不适当的访问并产生不合适的访问触发器，这导致停止在逻辑块内以及在相关系统模块中的处理。

9. 发明申请

US20080246746A1 DISPLAY CONTROLLER BLINKING MODE CIRCUITRY FOR LCD PANEL OF TWISTED NEMATIC TYPE 有权
标题翻译：显示控制器闪烁模式电路，用于双面类型的液晶面板
公开(公告)号：US20080246746A1
公开(公告)日：2008-10-09
申请号：US11696574
申请日：2007-04-04
申请人： Alain Vergnes , Sebastien Younes , Jerome Alingry
发明人： Alain Vergnes , Sebastien Younes , Jerome Alingry
IPC分类号： G06F3/038
CPC分类号： G09G3/3611 , G09G3/3614 , G09G3/3622 , G09G3/3696 , G09G2310/0278 , G09G2310/061 , G09G2330/021 , G09G2360/18
摘要： A display controller for providing signals to a discrete display panel unit comprising: a set of registers configured to hold data to be displayed; a first logic circuitry connected to the set of registers and configured to receive the data from the set of registers, generate the signal waveforms required by the display panel according to the data, and provide the signal waveforms to the display panel; a second logic circuitry connected to the first logic circuitry, the second logic circuitry configured to generate timing signals for timing the first logic circuitry providing the waveforms to the display panel; and a resistor ladder connected to the second logic circuitry, the resistor ladder configured to generate intermediate voltages required to drive the display panel, and configured to receive the timing signals, wherein the controller is configured to automatically and periodically disable the resistor ladder according to one of the timing signals.
摘要翻译：一种用于向分立显示面板单元提供信号的显示控制器，包括：一组寄存器，被配置为保存待显示的数据; 连接到所述一组寄存器并被配置为从所述寄存器组接收数据的第一逻辑电路，根据所述数据生成所述显示面板所需的信号波形，并将所述信号波形提供给所述显示面板; 连接到第一逻辑电路的第二逻辑电路，所述第二逻辑电路经配置以产生定时信号，用于将提供波形的第一逻辑电路定时到显示面板; 和连接到第二逻辑电路的电阻梯，电阻梯被配置为产生驱动显示面板所需的中间电压，并被配置为接收定时信号，其中控制器被配置为根据一个自动地和周期地禁用电阻梯的定时信号。

10. 发明申请

US20080123445A1 CIRCUITS TO DELAY A SIGNAL FROM DDR-SDRAM MEMORY DEVICE INCLUDING AN AUTOMATIC PHASE ERROR CORRECTION 有权
标题翻译：从DDR-SDRAM存储器设备延迟信号的电路，包括自动相位误差校正
公开(公告)号：US20080123445A1
公开(公告)日：2008-05-29
申请号：US11466327
申请日：2006-08-22
申请人： Alain Vergnes , Eric Matulik , Frederic Schumacher
发明人： Alain Vergnes , Eric Matulik , Frederic Schumacher
IPC分类号： G11C7/22
CPC分类号： G11C29/02 , G11C11/401 , G11C29/023 , G11C29/028 , G11C2029/0409
摘要： A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to relaize said first delay altered by the fraction number of delay elements.
摘要翻译：一种用于延迟控制信号的方法，包括接收时钟信号，确定产生等于时钟信号的周期的目标量的第一延迟所需的延迟元件的数量，接收具有在该时钟信号产生的边沿的数据信号时间作为控制信号的边缘，确定等于产生用于数据信号的第二延迟或控制信号对准其边缘所需的延迟元件的数量的分数，除以提供必需的级联延迟元件的数量延迟等于时钟信号的周期的目标量乘以延迟元件的数量以产生第一延迟，并且通过级联延迟元件的数量延迟控制信号，以使所述第一延迟改变为分数数的延迟元素。

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