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1. 发明授权

US08566628B2 North-bridge to south-bridge protocol for placing processor in low power state 有权
标题翻译：用于将处理器置于低功率状态的北桥南桥协议
公开(公告)号：US08566628B2
公开(公告)日：2013-10-22
申请号：US12436439
申请日：2009-05-06
申请人： Alexander Branover , Maurice B. Steinman , Ming L. So , Xiao Gang Zheng
发明人： Alexander Branover , Maurice B. Steinman , Ming L. So , Xiao Gang Zheng
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations.
摘要翻译：处理器集成电路具有一个或多个处理器核心和北桥中的功率管理控制器，其为一个或多个处理器核心生成第一功率状态推荐。北桥还从南桥集成电路获得了第二个功率状态建议。北桥基于第一和第二功率状态建议确定一个或多个处理器核的最终功率状态。

2. 发明申请

US20100287394A1 NORTH-BRIDGE TO SOUTH-BRIDGE PROTOCOL FOR PLACING PROCESSOR IN LOW POWER STATE 有权
标题翻译： “南桥”至“南桥”配置处理器在低功率状态
公开(公告)号：US20100287394A1
公开(公告)日：2010-11-11
申请号：US12436439
申请日：2009-05-06
申请人： Alexander Branover , Maurice B. Steinman , Ming L. So , Xiao Gang Zheng
发明人： Alexander Branover , Maurice B. Steinman , Ming L. So , Xiao Gang Zheng
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations.
摘要翻译：处理器集成电路具有一个或多个处理器核心和北桥中的功率管理控制器，其为一个或多个处理器核心生成第一功率状态推荐。北桥还从南桥集成电路获得了第二个功率状态建议。北桥基于第一和第二功率状态建议确定一个或多个处理器核的最终功率状态。

3. 发明授权

US09046915B2 Circuit and method for initializing a computer system 有权
标题翻译：用于初始化计算机系统的电路和方法
公开(公告)号：US09046915B2
公开(公告)日：2015-06-02
申请号：US13405957
申请日：2012-02-27
申请人： Xiao Gang Zheng , Ming L. So
发明人： Xiao Gang Zheng , Ming L. So
IPC分类号： G06F12/00 , G06F3/00 , G06F13/36 , G06F9/445 , G06F9/44
CPC分类号： G06F3/00 , G06F8/654 , G06F9/4411 , G06F9/445 , G06F13/36
摘要： A circuit for use in a computing system including a bus interface unit and an autoload controller. The autoload controller has an input to receive an initialization signal. In response to receiving the initialization signal, the autoload controller searches for a signature using the bus interface unit and, in response to finding the signature at a signature address, loads a plurality of base addresses corresponding to a plurality of controllers from memory locations having a predetermined relationship to the address, and provides the plurality of base addresses to a control output thereof.
摘要翻译：一种用于包括总线接口单元和自动加载控制器的计算系统的电路。自动加载控制器具有接收初始化信号的输入。响应于接收到初始化信号，自动加载控制器使用总线接口单元搜索签名，并且响应于在签名地址处找到签名，从具有多个控制器的存储器位置加载与多个控制器相对应的多个基地址与地址的预定关系，并将多个基地址提供给其控制输出。

4. 发明授权

US09423847B2 Method and apparatus for transitioning a system to an active disconnect state 有权
标题翻译：用于将系统转换到主动断开状态的方法和装置
公开(公告)号：US09423847B2
公开(公告)日：2016-08-23
申请号：US13332280
申请日：2011-12-20
申请人： Alexander J. Branover , Krishna S Bernucho , Maurice B Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P Shimizu , Gary H. Simpson , Laura M. Smith
发明人： Alexander J. Branover , Krishna S Bernucho , Maurice B Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P Shimizu , Gary H. Simpson , Laura M. Smith
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3206
摘要： A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.
摘要翻译：处理器包括处理器核心和功率管理控制器，其可操作以接收定时器事件，存储定时器事件，生成硬件系统睡眠命令以进入硬件系统睡眠状态，以及在退出硬件系统睡眠状态时恢复定时器事件。

5. 发明申请

US20130227196A1 CIRCUIT AND METHOD FOR INITIALIZING A COMPUTER SYSTEM 有权
标题翻译：用于初始化计算机系统的电路和方法
公开(公告)号：US20130227196A1
公开(公告)日：2013-08-29
申请号：US13405957
申请日：2012-02-27
申请人： Xiao Gang Zheng , Ming L. So
发明人： Xiao Gang Zheng , Ming L. So
IPC分类号： G06F12/00 , G06F3/00 , G06F13/36
CPC分类号： G06F3/00 , G06F8/654 , G06F9/4411 , G06F9/445 , G06F13/36
摘要： A circuit for use in a computing system including and a bus interface unit and an autoload controller. The autoload controller has an input to receive an initialization signal. In response to receiving the initialization signal, autoload controller searches for a signature using the bus interface unit and, in response to finding the signature at a signature address, loads a plurality of base addresses corresponding to a plurality of controllers from memory locations having a predetermined relationship to the address, and provides the plurality of base addresses to a control output thereof.
摘要翻译：一种用于计算系统的电路，包括总线接口单元和自动加载控制器。自动加载控制器具有接收初始化信号的输入。响应于接收到初始化信号，自动加载控制器使用总线接口单元搜索签名，并且响应于在签名地址处找到签名，从具有预定的存储位置的存储器位置加载与多个控制器相对应的多个基地址与地址的关系，并将多个基地址提供给其控制输出。

6. 发明申请

US20130159750A1 METHOD AND APPARATUS FOR TRANSITIONING A SYSTEM TO AN ACTIVE DISCONNECT STATE 有权
标题翻译：将系统过渡到活动断开状态的方法和装置
公开(公告)号：US20130159750A1
公开(公告)日：2013-06-20
申请号：US13332280
申请日：2011-12-20
申请人： Alexander J. Branover , Krishna S. Bernucho , Maurice B. Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L. Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P. Shimizu , Gary H. Simpson , Laura M. Smith
发明人： Alexander J. Branover , Krishna S. Bernucho , Maurice B. Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L. Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P. Shimizu , Gary H. Simpson , Laura M. Smith
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3206
摘要： A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.
摘要翻译：处理器包括处理器核心和功率管理控制器，其可操作以接收定时器事件，存储定时器事件，生成硬件系统睡眠命令以进入硬件系统睡眠状态，以及在退出硬件系统睡眠状态时恢复定时器事件。

7. 发明授权

US08433936B2 USB power conservation method and apparatus 有权
标题翻译： USB节能方法和装置
公开(公告)号：US08433936B2
公开(公告)日：2013-04-30
申请号：US12270748
申请日：2008-11-13
申请人： Ming L. So , Kenny Xu
发明人： Ming L. So , Kenny Xu
IPC分类号： G06F1/26
CPC分类号： G06F1/3215
摘要： Embodiments of a method and system for conserving power used in a central processing unit (CPU) are described. An embodiment uses direct memory access (DMA) fetch suspend logic to allow the CPU to stay in a sleep state indefinitely until a break event occurs. Embodiments include power management monitoring and Universal Serial Bus (USB) descriptor monitoring logic. Power management monitor logic monitors the CPU sleep state and sets a status flag to the USB descriptor monitoring logic whenever the CPU is in a predefined sleep state. The USB descriptor monitoring logic monitors the fetching of linked descriptor lists. When the CPU status flag is raised, it causes monitoring of the descriptor fetch by the USB descriptor monitoring logic. If the USB controller has completed all of the descriptor fetches while the CPU sleep flag is true, this logic sets a flag to cause the USB controller to suspend DMA fetch operations.
摘要翻译：描述了用于节省用于中央处理单元（CPU）的功率的方法和系统的实施例。一个实施例使用直接存储器访问（DMA）提取暂停逻辑来允许CPU无限期地保持在休眠状态，直到发生中断事件。实施例包括电源管理监视和通用串行总线（USB）描述符监视逻辑。电源管理监视器逻辑监视CPU休眠状态，并且每当CPU处于预定义的睡眠状态时，将状态标志设置为USB描述符监视逻辑。 USB描述符监视逻辑监视链接描述符列表的获取。当CPU状态标志出现时，它会引起USB描述符监视逻辑对描述符提取的监视。如果USB控制器在CPU休眠标志为真时完成了所有描述符提取，则此逻辑将设置一个标志，以使USB控制器挂起DMA提取操作。

8. 发明申请

US20140136738A1 EMULATED LEGACY BUS OPERATION OVER A BIT-SERIAL BUS 有权
标题翻译：模拟总线在一个BIT串行总线上运行
公开(公告)号：US20140136738A1
公开(公告)日：2014-05-15
申请号：US13678132
申请日：2012-11-15
申请人： Scott E. Matlock , Ming L. So
发明人： Scott E. Matlock , Ming L. So
IPC分类号： G06F13/36
CPC分类号： G06F13/4282 , G06F13/387 , G06F13/4027
摘要： Legacy bus operations, such as x86 I/O instructions having an address space separate from memory address space, are supported in a system in which I/O devices are coupled to a microcontroller connected via an SPI bus or other bit-serial bus. Each legacy bus operation is recognized and trapped by an interface controller, such as a south-bridge controller, which maps the trapped legacy bus operation into a corresponding bit-serial bus transaction, and transacts this corresponding bit-serial bus transaction on the bit-serial bus. Existing software infrastructure using x86 I/O instructions can remain intact, with I/O transactions bound for the SPI bus.
摘要翻译：在其中I / O设备耦合到通过SPI总线或其他位串行总线连接的微控制器的系统中，传统总线操作（例如具有与存储器地址空间不同的地址空间的x86 I / O指令）支持。每个传统总线操作被诸如南桥控制器的接口控制器识别和捕获，该桥接器控制器将被捕获的传统总线操作映射到对应的位串行总线事务中，并且将该对应的比特串行总线事务处理在位 - 串行总线使用x86 I / O指令的现有软件架构可以保持不变，I / O事务限制为SPI总线。

9. 发明申请

US20090254771A1 USB Power Conservation Method and Apparatus 有权
标题翻译： USB节能方法与装置
公开(公告)号：US20090254771A1
公开(公告)日：2009-10-08
申请号：US12270748
申请日：2008-11-13
申请人： Ming L. So , Kenny Xu
发明人： Ming L. So , Kenny Xu
IPC分类号： G06F1/32 , G06F13/00
CPC分类号： G06F1/3215
摘要： Embodiments of a method and system for conserving power used in a central processing unit (CPU) are described. An embodiment uses direct memory access (DMA) fetch suspend logic to allow the CPU to stay in a sleep state indefinitely until a break event occurs. Embodiments include power management monitoring and Universal Serial Bus (USB) descriptor monitoring logic. Power management monitor logic monitors the CPU sleep state and sets a status flag to the USB descriptor monitoring logic whenever the CPU is in a predefined sleep state. The USB descriptor monitoring logic monitors the fetching of linked descriptor lists. When the CPU status flag is raised, it causes monitoring of the descriptor fetch by the USB descriptor monitoring logic. If the USB controller has completed all of the descriptor fetches while the CPU sleep flag is true, this logic sets a flag to cause the USB controller to suspend DMA fetch operations.
摘要翻译：描述了用于节省用于中央处理单元（CPU）的功率的方法和系统的实施例。一个实施例使用直接存储器访问（DMA）提取暂停逻辑来允许CPU无限期地保持在休眠状态，直到发生中断事件。实施例包括电源管理监视和通用串行总线（USB）描述符监视逻辑。电源管理监视器逻辑监视CPU休眠状态，并且每当CPU处于预定义的睡眠状态时，将状态标志设置为USB描述符监视逻辑。 USB描述符监视逻辑监视链接描述符列表的获取。当CPU状态标志出现时，它会引起USB描述符监视逻辑对描述符提取的监视。如果USB控制器在CPU休眠标志为真时完成了所有描述符提取，则此逻辑将设置一个标志，以使USB控制器挂起DMA提取操作。

10. 发明授权

US09858235B2 Emulated legacy bus operation over a bit-serial bus 有权
公开(公告)号：US09858235B2
公开(公告)日：2018-01-02
申请号：US13678132
申请日：2012-11-15
申请人： Scott E. Matlock , Ming L. So
发明人： Scott E. Matlock , Ming L. So
IPC分类号： G06F13/36 , G06F13/42 , G06F13/38 , G06F13/40 , G06F11/26
CPC分类号： G06F13/4282 , G06F13/387 , G06F13/4027
摘要： Legacy bus operations, such as x86 I/O instructions having an address space separate from memory address space, are supported in a system in which I/O devices are coupled to a microcontroller connected via an SPI bus or other bit-serial bus. Each legacy bus operation is recognized and trapped by an interface controller, such as a south-bridge controller, which maps the trapped legacy bus operation into a corresponding bit-serial bus transaction, and transacts this corresponding bit-serial bus transaction on the bit-serial bus. Existing software infrastructure using x86 I/O instructions can remain intact, with I/O transactions bound for the SPI bus.

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