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1. 发明授权

US08589836B2 Formally checking equivalence using equivalence relationships 有权
标题翻译：使用等价关系正式检查等价
公开(公告)号：US08589836B2
公开(公告)日：2013-11-19
申请号：US12112940
申请日：2008-04-30
申请人： Alfred Koelbl , Carl Preston Pixley
发明人： Alfred Koelbl , Carl Preston Pixley
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts [t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving that propagates symbolic values indicative of whether a node carries the same data content as another node. The theorem proving starts from initial conditions for HLMts [t] determined by partial execution of the HLM. Propagation to a combinational function output can be determined from equivalence relationships between it and another combinational function. Propagation through a multiplexer can produce a conditional symbolic value.
摘要翻译：提出了一种用于正式比较RTLM和HLM的等效性测试系统。 RTLM和HLM首先转换为DFG RTLMDFG和HLMDFG。然后将RTLMDFG和HLMDFG置于时间步骤中，称为RTLMts和HLMts。选择耦合RTLMts和HLMts的测试台CSts。 RTLMts [t]，HLMts [t]和CSts [t]的组合可以将部件指定为数据路径。指定为数据路径的部分可以受到等效性检查的形式的限制，其通过归纳定理的形式来证明等价性，证明传播指示节点是否携带与另一节点相同的数据内容的符号值。定理证明从HLMts的初始条件开始，通过HLM的部分执行确定。传播到组合函数输出可以从它与另一个组合函数之间的等价关系来确定。通过复用器的传播可以产生条件符号值。

2. 发明授权

US08079000B2 Method and apparatus for performing formal verification using data-flow graphs 有权
标题翻译：使用数据流图进行形式验证的方法和装置
公开(公告)号：US08079000B2
公开(公告)日：2011-12-13
申请号：US12188978
申请日：2008-08-08
申请人： Alfred Koelbl , Carl Preston Pixley
发明人： Alfred Koelbl , Carl Preston Pixley
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/504
摘要： An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts[t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving that propagates symbolic values indicative of whether a node carries the same data content as another node. The theorem proving starts from initial conditions for HLMts[t] determined by partial execution of the HLM. Propagation to a combinational function output can be determined from equivalence relationships between it and another combinational function. Propagation through a multiplexer can produce a conditional symbolic value.
摘要翻译：提出了一种用于正式比较RTLM和HLM的等效性测试系统。 RTLM和HLM首先转换为DFG RTLMDFG和HLMDFG。然后将RTLMDFG和HLMDFG置于时间步骤中，称为RTLMts和HLMts。选择耦合RTLMts和HLMts的测试台CSts。 RTLMts [t]，HLMts [t]和CSts [t]的组合可以将部件指定为数据路径。指定为数据路径的部分可以受到等效性检查的形式的限制，其通过归纳定理的形式来证明等价性，证明传播指示节点是否携带与另一节点相同的数据内容的符号值。定理证明从HLMts的初始条件开始，通过HLM的部分执行确定。传播到组合函数输出可以从它与另一个组合函数之间的等价关系来确定。通过复用器的传播可以产生条件符号值。

3. 发明申请

US20110276934A1 FORMAL EQUIVALENCE CHECKING BETWEEN TWO MODELS OF A CIRCUIT DESIGN USING CHECKPOINTS 有权
标题翻译：使用检查点的电路设计的两种模型之间的形式等效检查
公开(公告)号：US20110276934A1
公开(公告)日：2011-11-10
申请号：US12775063
申请日：2010-05-06
申请人： Alfred Koelbl
发明人： Alfred Koelbl
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Some embodiments of the present invention provide techniques and systems for determining whether a high-level model (HLM) for a circuit design is equivalent to a register-transfer-level (RTL) model for the circuit design. During operation, a system can identify a set of checkpoints. Each checkpoint can be associated with a characteristic function defined over the states of a finite-state-machine (FSM) representation of the HLM, a characteristic function defined over the states of an FSM representation of the RTL model, and an invariant defined over a set of variables in the HLM and a set of registers in the RTL model. Next, the system can generate a set of invariant proof problems, wherein each invariant proof problem corresponds to a transition between two checkpoints in the set of checkpoints. The system can then determine whether the HLM is equivalent to the RTL model by solving the set of invariant proof problems.
摘要翻译：本发明的一些实施例提供用于确定用于电路设计的高级模型（HLM）是否等于电路设计的寄存器传送级（RTL）模型的技术和系统。在操作期间，系统可以识别一组检查点。每个检查点可以与通过HLM的有限状态机（FSM）表示的状态定义的特征函数相关联，这是在RTL模型的FSM表示的状态上定义的特征函数，以及在 HLM中的一组变量和RTL模型中的一组寄存器。接下来，系统可以生成一组不变性证明问题，其中每个不变校验问题对应于检查点集合中两个检查点之间的转换。然后，系统可以通过求解一组不变量证明问题来确定HLM是否等同于RTL模型。

4. 发明授权

US07260800B1 Method and apparatus for initial state extraction 有权
标题翻译：初始状态提取的方法和装置
公开(公告)号：US07260800B1
公开(公告)日：2007-08-21
申请号：US11149827
申请日：2005-06-10
申请人： Alfred Koelbl , Carl Preston Pixley
发明人： Alfred Koelbl , Carl Preston Pixley
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts[t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving. The theorem proving starts from initial conditions for HLMts[t] determined by partial execution of the HLM. The user specifies a location within the HLM where initialization is finished. The HLM is executed, with procedure calls related to memory allocation intercepted and allocation information collected. The initialization techniques can be used with any formal analysis tool operating on representations derived from an HLM.
摘要翻译：提出了一种用于正式比较RTLM和HLM的等效性测试系统。首先将RTLM和HLM转换为DFG RTLM DFG和HLM DFG 。然后将RTLM DFG和HLM DFG 放入时间步长形式，称为RTLM 和HLM 。选择了耦合RTLM 和HLM 的测试台CS 。 RTLM [t]，HLM t和CS [t]的组合可以将部件指定为数据通路。指定为数据路径的部分可以采用等价检查的形式，以通过归纳定理证明的形式来证明等价性。定理证明从通过HLM的部分执行确定的HLM 的初始条件开始。用户指定HLM内的初始化完成的位置。执行HLM，并且收集与内存分配相关的过程调用和分配信息。初始化技术可以用于对从HLM派生的表示进行操作的任何形式分析工具。

5. 发明授权

US08201119B2 Formal equivalence checking between two models of a circuit design using checkpoints 有权
标题翻译：使用检查点的电路设计的两个模型之间的正式等价检查
公开(公告)号：US08201119B2
公开(公告)日：2012-06-12
申请号：US12775063
申请日：2010-05-06
申请人： Alfred Koelbl
发明人： Alfred Koelbl
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Some embodiments of the present invention provide techniques and systems for determining whether a high-level model (HLM) for a circuit design is equivalent to a register-transfer-level (RTL) model for the circuit design. During operation, a system can identify a set of checkpoints. Each checkpoint can be associated with a characteristic function defined over the states of a finite-state-machine (FSM) representation of the HLM, a characteristic function defined over the states of an FSM representation of the RTL model, and an invariant defined over a set of variables in the HLM and a set of registers in the RTL model. Next, the system can generate a set of invariant proof problems, wherein each invariant proof problem corresponds to a transition between two checkpoints in the set of checkpoints. The system can then determine whether the HLM is equivalent to the RTL model by solving the set of invariant proof problems.
摘要翻译：本发明的一些实施例提供用于确定用于电路设计的高级模型（HLM）是否等于电路设计的寄存器传送级（RTL）模型的技术和系统。在操作期间，系统可以识别一组检查点。每个检查点可以与通过HLM的有限状态机（FSM）表示的状态定义的特征函数相关联，这是在RTL模型的FSM表示的状态上定义的特征函数，以及在 HLM中的一组变量和RTL模型中的一组寄存器。接下来，系统可以生成一组不变性证明问题，其中每个不变校验问题对应于检查点集合中两个检查点之间的转换。然后，系统可以通过求解一组不变量证明问题来确定HLM是否等同于RTL模型。

6. 发明授权

US07509604B1 Method and apparatus for formally comparing stream-based designs 有权
标题翻译：用于正式比较基于流的设计的方法和装置
公开(公告)号：US07509604B1
公开(公告)日：2009-03-24
申请号：US11149852
申请日：2005-06-10
申请人： Alfred Koelbl , Carl Preston Pixley
发明人： Alfred Koelbl , Carl Preston Pixley
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/504
摘要： An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts[t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving. The theorem proving starts from initial conditions for HLMts[t] determined by partial execution of the HLM. A CSts for proving stream-based equivalence is presented. The CSts operates by allowing one DFG to process data as soon as it can, while not guaranteeing the same for a second DFG. The stream-based combining structure can be used in with any formal analysis tool.
摘要翻译：提出了一种用于正式比较RTLM和HLM的等效性测试系统。 RTLM和HLM首先转换为DFG RTLMDFG和HLMDFG。然后将RTLMDFG和HLMDFG置于时间步骤中，称为RTLMts和HLMts。选择耦合RTLMts和HLMts的测试台CSts。 RTLMts [t]，HLMts [t]和CSts [t]的组合可以将部件指定为数据路径。指定为数据路径的部分可以采用等价检查的形式，以通过归纳定理证明的形式来证明等价性。定理证明从HLMts的初始条件开始，通过HLM的部分执行确定。提出了一种用于证明基于流的等价性的CSts。 CSts通过允许一个DFG尽可能快地处理数据，但不保证第二个DFG保持一致。基于流的组合结构可以与任何形式的分析工具一起使用。

7. 发明授权

US07509599B1 Method and apparatus for performing formal verification using data-flow graphs 有权
标题翻译：使用数据流图进行形式验证的方法和装置
公开(公告)号：US07509599B1
公开(公告)日：2009-03-24
申请号：US11150685
申请日：2005-06-10
申请人： Alfred Koelbl , Carl Preston Pixley
发明人： Alfred Koelbl , Carl Preston Pixley
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts[t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving. The theorem proving starts from initial conditions for HLMts[t] determined by partial execution of the HLM. CSts can be selected depending upon a classification of RTLMts and HLMts. Techniques for classifying RTLMts and HLMts, and for selecting a suitable CSts, are presented. The classifications can operate on non-DFG representations. The CSts generation techniques can be used with any formal analysis technique.
摘要翻译：提出了一种用于正式比较RTLM和HLM的等效性测试系统。 RTLM和HLM首先转换为DFG RTLMDFG和HLMDFG。然后将RTLMDFG和HLMDFG置于时间步骤中，称为RTLMts和HLMts。选择耦合RTLMts和HLMts的测试台CSts。 RTLMts [t]，HLMts [t]和CSts [t]的组合可以将部件指定为数据路径。指定为数据路径的部分可以采用等价检查的形式，以通过归纳定理证明的形式来证明等价性。定理证明从HLMts的初始条件开始，通过HLM的部分执行确定。可以根据RTLMts和HLMts的分类来选择CSts。介绍了分类RTLMts和HLMts以及选择合适的CSts的技术。分类可以对非DFG表示进行操作。 CSts生成技术可以与任何形式的分析技术一起使用。

8. 发明申请

US20080235253A1 METHOD AND APPARATUS FOR FORMALLY CHECKING EQUIVALENCE USING EQUIVALENCE RELATIONSHIPS 有权
标题翻译：使用等价关系正式检查等价的方法和装置
公开(公告)号：US20080235253A1
公开(公告)日：2008-09-25
申请号：US12112996
申请日：2008-04-30
申请人： Alfred Koelbl , Carl Preston Pixley
发明人： Alfred Koelbl , Carl Preston Pixley
IPC分类号： G06F17/30
CPC分类号： G06F17/504
摘要： An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts[t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving that propagates symbolic values indicative of whether a node carries the same data content as another node. The theorem proving starts from initial conditions for HLMts[t] determined by partial execution of the HLM. Propagation to a combinational function output can be determined from equivalence relationships between it and another combinational function. Propagation through a multiplexer can produce a conditional symbolic value.
摘要翻译：提出了一种用于正式比较RTLM和HLM的等效性测试系统。首先将RTLM和HLM转换为DFG RTLM DFG和HLM DFG 。然后将RTLM DFG和HLM DFG 放入时间步长形式，称为RTLM 和HLM 。选择了耦合RTLM 和HLM 的测试台CS 。 RTLM [t]，HLM t和CS [t]的组合可以将部件指定为数据通路。指定为数据路径的部分可以受到等效性检查的形式的限制，其通过归纳定理的形式来证明等价性，证明传播指示节点是否携带与另一节点相同的数据内容的符号值。定理证明从通过HLM的部分执行确定的HLM 的初始条件开始。传播到组合函数输出可以从它与另一个组合函数之间的等价关系来确定。通过复用器的传播可以产生条件符号值。

9. 发明申请

US20080209370A1 FORMALLY PROVING THE FUNCTIONAL EQUIVALENCE OF PIPELINED DESIGNS CONTAINING MEMORIES 有权
标题翻译：正式提供包含记忆的管道设计的功能等效性
公开(公告)号：US20080209370A1
公开(公告)日：2008-08-28
申请号：US12112896
申请日：2008-04-30
申请人： Alfred Koelbl , Jerry Burch , Carl Pixley
发明人： Alfred Koelbl , Jerry Burch , Carl Pixley
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： One embodiment of the present invention provides a system that formally proves the functional equivalence of pipelined designs. First, the system receives a specification for a first pipelined design, which includes a first memory system, and a specification for a second pipelined design, which includes a second memory system. Next, the system determines a correspondence between operations on the first memory system and corresponding operations on the second memory system. This correspondence enables memory operations to be represented in a combinational form based on design inputs, thereby allowing both memory systems to be logically abstracted out of their respective designs. After the memory systems have been abstracted out, the system compares the combinational outputs of the first pipelined design and the combinational outputs of the second pipelined design to verify that the designs are functionally equivalent.
摘要翻译：本发明的一个实施例提供了正式证明流水线设计的功能等同性的系统。首先，系统接收第一流水线设计的规范，其包括第一存储器系统和包括第二存储器系统的第二流水线设计的规范。接下来，系统确定第一存储器系统上的操作与第二存储器系统上的相应操作之间的对应关系。这种对应使得能够基于设计输入以组合形式表示存储器操作，从而允许两个存储器系统在它们各自的设计中被逻辑地抽象出来。在将存储器系统抽象出来之后，系统将第一流水线设计的组合输出与第二流水线设计的组合输出进行比较，以验证设计在功能上是等效的。

10. 发明授权

US08001500B2 Method and apparatus for formally checking equivalence using equivalence relationships 有权
标题翻译：使用等价关系正式检查等价的方法和装置
公开(公告)号：US08001500B2
公开(公告)日：2011-08-16
申请号：US12112996
申请日：2008-04-30
申请人： Alfred Koelbl , Carl Preston Pixley
发明人： Alfred Koelbl , Carl Preston Pixley
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts[t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving that propagates symbolic values indicative of whether a node carries the same data content as another node. The theorem proving starts from initial conditions for HLMts[t] determined by partial execution of the HLM. Propagation to a combinational function output can be determined from equivalence relationships between it and another combinational function. Propagation through a multiplexer can produce a conditional symbolic value.
摘要翻译：提出了一种用于正式比较RTLM和HLM的等效性测试系统。 RTLM和HLM首先转换为DFG RTLMDFG和HLMDFG。然后将RTLMDFG和HLMDFG置于时间步骤中，称为RTLMts和HLMts。选择耦合RTLMts和HLMts的测试台CSts。 RTLMts [t]，HLMts [t]和CSts [t]的组合可以将部件指定为数据路径。指定为数据路径的部分可以受到等效性检查的形式的限制，其通过归纳定理的形式来证明等价性，证明传播指示节点是否携带与另一节点相同的数据内容的符号值。定理证明从HLMts的初始条件开始，通过HLM的部分执行确定。传播到组合函数输出可以从它与另一个组合函数之间的等价关系来确定。通过复用器的传播可以产生条件符号值。

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