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1. 发明申请

US20160380073A1 NORMALLY OFF GALLIUM NITRIDE FIELD EFFECT TRANSISTORS (FET) 有权
标题翻译：氮化镓场效应晶体管（FET）
公开(公告)号：US20160380073A1
公开(公告)日：2016-12-29
申请号：US14729396
申请日：2015-06-03
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Anup Bhalla , Tinggang Zhu
IPC分类号： H01L29/66
CPC分类号： H01L29/7786 , H01L29/1029 , H01L29/2003 , H01L29/402 , H01L29/408 , H01L29/41725 , H01L29/42356 , H01L29/66462 , H01L29/778 , H01L29/7783 , H01L29/7785 , H01L29/7787 , H01L29/785 , H01L29/788
摘要： A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.
摘要翻译：异质结构场效应晶体管（HFET）氮化镓（GaN）半导体功率器件包括异质结结构，其包括与两个不同带隙的第二半导体层接口的第一半导体层，从而产生作为二维电子气的界面层（2DEG ）层。功率器件还包括设置在异质结结构的顶部上的栅电极的两个相对侧上的源电极和漏电极，用于控制2DEG层中的源电极和漏电极之间的电流。功率器件还包括位于栅电极和异质结结构之间的浮置栅极，其中栅电极与浮置栅极绝缘，并具有绝缘层，并且其中浮置栅极位于上方并且填充有来自异质结的薄绝缘层并且其中浮置栅极被充电用于连续施加电压到2DEG层以夹紧在源极和漏极之间的2DEG层中流动的电流，由此HFET半导体功率器件是常闭装置。

2. 发明申请

US20180308967A1 NORMALLY OFF GALLIUM NITRIDE FIELD EFFECT TRANSISTORS (FET) 审中-公开
公开(公告)号：US20180308967A1
公开(公告)日：2018-10-25
申请号：US16019979
申请日：2018-06-27
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Anup Bhalla , Tinggang Zhu
IPC分类号： H01L29/778 , H01L29/788 , H01L29/66 , H01L29/20 , H01L29/40 , H01L29/423 , H01L29/10 , H01L29/417 , H01L29/78
CPC分类号： H01L29/7786 , H01L29/1029 , H01L29/2003 , H01L29/402 , H01L29/408 , H01L29/41725 , H01L29/42356 , H01L29/66462 , H01L29/778 , H01L29/7783 , H01L29/7785 , H01L29/7787 , H01L29/785 , H01L29/788
摘要： A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.

3. 发明授权

US10439058B2 Normally off gallium nitride field effect transistors (FET) 有权
公开(公告)号：US10439058B2
公开(公告)日：2019-10-08
申请号：US16019979
申请日：2018-06-27
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Anup Bhalla , Tinggang Zhu
IPC分类号： H01L29/778 , H01L29/40 , H01L29/66 , H01L29/20 , H01L29/788 , H01L29/10 , H01L29/423 , H01L29/417 , H01L29/78
摘要： A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.

4. 发明授权

US10170563B2 Gallium nitride semiconductor device with improved termination scheme 有权
公开(公告)号：US10170563B2
公开(公告)日：2019-01-01
申请号：US13763649
申请日：2013-02-09
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Tinggang Zhu
IPC分类号： H01L29/20 , H01L29/872 , H01L29/66 , H01L29/06
摘要： This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein.

5. 发明授权

US09520480B1 Normally off gallium nitride field effect transistors (FET) 有权
标题翻译：通常关闭氮化镓场效应晶体管（FET）
公开(公告)号：US09520480B1
公开(公告)日：2016-12-13
申请号：US14729396
申请日：2015-06-03
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Anup Bhalla , Tinggang Zhu
IPC分类号： H01L21/338 , H01L29/66 , H01L29/10 , H01L29/778 , H01L29/40 , H01L29/417 , H01L29/788 , H01L29/78 , H01L29/20
CPC分类号： H01L29/7786 , H01L29/1029 , H01L29/2003 , H01L29/402 , H01L29/408 , H01L29/41725 , H01L29/42356 , H01L29/66462 , H01L29/778 , H01L29/7783 , H01L29/7785 , H01L29/7787 , H01L29/785 , H01L29/788
摘要： A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.
摘要翻译：异质结构场效应晶体管（HFET）氮化镓（GaN）半导体功率器件包括异质结结构，其包括与两个不同带隙的第二半导体层接口的第一半导体层，从而产生作为二维电子气的界面层（2DEG ）层。功率器件还包括设置在异质结结构的顶部上的栅电极的两个相对侧上的源电极和漏电极，用于控制2DEG层中的源电极和漏电极之间的电流。功率器件还包括位于栅电极和异质结结构之间的浮置栅极，其中栅电极与浮置栅极绝缘，并具有绝缘层，并且其中浮置栅极位于上方并且填充有来自异质结的薄绝缘层并且其中浮置栅极被充电用于连续施加电压到2DEG层以夹紧在源极和漏极之间的2DEG层中流动的电流，由此HFET半导体功率器件是常闭装置。

6. 发明授权

US09064945B2 Normally off gallium nitride field effect transistors (FET) 有权
标题翻译：通常关闭氮化镓场效应晶体管（FET）
公开(公告)号：US09064945B2
公开(公告)日：2015-06-23
申请号：US13726102
申请日：2012-12-22
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Anup Bhalla , Tinggang Zhu
IPC分类号： H01L29/778 , H01L29/66 , H01L29/40 , H01L29/20 , H01L29/10
CPC分类号： H01L29/7786 , H01L29/1029 , H01L29/2003 , H01L29/402 , H01L29/408 , H01L29/41725 , H01L29/42356 , H01L29/66462 , H01L29/778 , H01L29/7783 , H01L29/7785 , H01L29/7787 , H01L29/785 , H01L29/788
摘要： A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero-junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.
摘要翻译：异质结场效应晶体管（HFET）氮化镓（GaN）半导体功率器件包括异质结结构，其包括与两个不同带隙的第二半导体层接口的第一半导体层，从而产生作为二维电子气的界面层 2DEG）层。功率器件还包括设置在异质结结构的顶部上的栅电极的两个相对侧上的源电极和漏电极，用于控制2DEG层中的源电极和漏电极之间的电流。功率器件还包括位于栅电极和异质结结构之间的浮动栅极，其中栅电极与浮栅绝缘，并具有绝缘层，并且其中浮置栅极位于上方并且填充有薄绝缘层异质结结构，并且其中浮置栅极被充电以连续地向2DEG层施加电压以夹紧在源极和漏极之间的2DEG层中流动的电流，由此HFET半导体功率器件是常闭装置。

7. 发明授权

US10177221B2 Integrated Schottky diode in high voltage semiconductor device 有权
公开(公告)号：US10177221B2
公开(公告)日：2019-01-08
申请号：US15878381
申请日：2018-01-23
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Lingpeng Guan , Anup Bhalla , Madhur Bobde , Tinggang Zhu
IPC分类号： H01L29/78 , H01L29/739 , H01L29/06 , H01L29/66 , H01L29/872 , H01L29/10 , H01L29/49 , H01L29/40 , H01L29/423 , H01L29/08 , H01L29/51
摘要： This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

8. 发明授权

US10020389B2 Normally off gallium nitride field effect transistors (FET) 有权
公开(公告)号：US10020389B2
公开(公告)日：2018-07-10
申请号：US15365931
申请日：2016-11-30
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Anup Bhalla , Tinggang Zhu
IPC分类号： H01L29/66 , H01L29/778 , H01L29/40 , H01L29/20 , H01L29/788 , H01L29/10 , H01L29/423 , H01L29/417 , H01L29/78
CPC分类号： H01L29/7786 , H01L29/1029 , H01L29/2003 , H01L29/402 , H01L29/408 , H01L29/41725 , H01L29/42356 , H01L29/66462 , H01L29/778 , H01L29/7783 , H01L29/7785 , H01L29/7787 , H01L29/785 , H01L29/788
摘要： A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero-junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.

9. 发明申请

US20180212022A1 INTEGRATED SCHOTTKY DIODE IN HIGH VOLTAGE SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180212022A1
公开(公告)日：2018-07-26
申请号：US15878381
申请日：2018-01-23
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Lingpeng Guan , Anup Bhalla , Madhur Bobde , Tinggang Zhu
IPC分类号： H01L29/06 , H01L29/872 , H01L29/78 , H01L29/10 , H01L29/739 , H01L29/49
CPC分类号： H01L29/0634 , H01L29/0619 , H01L29/0834 , H01L29/1095 , H01L29/404 , H01L29/42368 , H01L29/4916 , H01L29/512 , H01L29/66333 , H01L29/66712 , H01L29/7393 , H01L29/7395 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

10. 发明申请

US20180182853A9 GALLIUM NITRIDE SEMICONDUCTOR DEVICE WITH IMPROVED TERMINATION SCHEME 审中-公开
公开(公告)号：US20180182853A9
公开(公告)日：2018-06-28
申请号：US13763649
申请日：2013-02-09
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Tinggang Zhu
IPC分类号： H01L29/20 , H01L29/872
CPC分类号： H01L29/2003 , H01L29/0619 , H01L29/66212 , H01L29/872
摘要： This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein.

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