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    • 5. 发明申请
    • NETWORK FUNCTIONS VIRTUALIZATION PLATFORMS WITH FUNCTION CHAINING CAPABILITIES
    • 网络功能具有功能链接能力的虚拟化平台
    • US20160321094A1
    • 2016-11-03
    • US14698636
    • 2015-04-28
    • Altera Corporation
    • Abdel Hafiz RabiAllen ChenMark Jonathan LewisJiefan Zhang
    • G06F9/455G06F13/28G06F13/40
    • G06F9/45558G06F13/28G06F13/4022G06F2009/45595G06F2213/0038G06F2213/28
    • A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.
    • 提供了网络功能虚拟化(NFV)的虚拟化平台。 虚拟化平台可以包括耦合到加速协处理器的主机处理器。 加速协处理器可以是可重构集成电路,以帮助为NFV提供改进的灵活性和敏捷性。 协处理器可以包括多个虚拟功能硬件加速模块,每个虚拟功能硬件加速模块被配置为执行相应的加速器功能。 在主处理器上运行的虚拟机可能希望在给定数据上在协处理器上连续执行多个加速器功能。 在一种合适的布置中,由加速器功能中的每一个输出的中间数据可以被反馈给主处理器。 在另一种合适的布置中,连续功能调用可以链接在一起,使得只有最终的结果数据被反馈到主机处理器。
    • 6. 发明授权
    • Methods for operating configurable storage and processing blocks at double and single data rates
    • 以双重和单数据速率运行可配置存储和处理块的方法
    • US09385724B1
    • 2016-07-05
    • US14045658
    • 2013-10-03
    • Altera Corporation
    • Herman SchmitJiefan Zhang
    • G06F1/00H03K19/173H03K3/02G11C7/10
    • H03K19/1737G11C7/10G11C7/1045G11C7/106G11C7/22H03K3/02H03K19/173H03K19/17736H03K19/1776
    • Integrated circuits such as application specific circuits or programmable logic devices may include specialized blocks such as configurable storage blocks and configurable processing blocks. Such specialized blocks may be controlled by clock signals and operated at single data rate or at double data rate. For instance, configurable storage blocks may be configured to use a double data rate communications scheme or a single data rate communication scheme to communicate data with other blocks. Configurable processing blocks may be configured to process data at a double data rate or a single data rate. Furthermore, configurable processing blocks that include accumulator circuitry may be configured to perform one accumulation at a single data rate or at a double data rate. Such configurable processing blocks may also be configured to perform two accumulations at a single data rate.
    • 诸如专用电路或可编程逻辑器件的集成电路可以包括诸如可配置存储块和可配置处理块的专用块。 这种专用块可以由时钟信号控制,并以单数据速率或双数据速率运行。 例如,可配置的存储块可以被配置为使用双数据速率通信方案或单个数据速率通信方案来与其他块通信数据。 可配置处理块可以被配置为以双数据速率或单个数据速率处理数据。 此外,包括累加器电路的可配置处理块可以被配置为以单数据速率或双倍数据速率执行一次累加。 这种可配置处理块还可以被配置为以单个数据速率执行两次累加。