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1. 发明授权

US08750026B1 Integrated circuits with asymmetric and stacked transistors 有权
标题翻译：具有不对称和堆叠晶体管的集成电路
公开(公告)号：US08750026B1
公开(公告)日：2014-06-10
申请号：US13923276
申请日：2013-06-20
申请人： Altera Corporation
发明人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
IPC分类号： G11C11/412 , G11C7/10 , G11C8/16
CPC分类号： G11C11/412
摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.
摘要翻译：不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。两个晶体管的栅极也连接在一起。两个晶体管可以具有不同的阈值电压。位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。不对称晶体管也可用于存储器单元中以减少泄漏。

2. 发明申请

US20160232952A9 Integrated Circuits with Asymmetric and Stacked Transistors 审中-公开
公开(公告)号：US20160232952A9
公开(公告)日：2016-08-11
申请号：US14268183
申请日：2014-05-02
申请人： Altera Corporation
发明人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
IPC分类号： G11C7/10 , G11C5/06
CPC分类号： H01L27/1104 , G11C5/06 , G11C7/1051 , G11C11/412 , H01L21/26586 , H01L21/266 , H01L21/82345 , H01L29/1045 , H01L29/4983 , H01L29/66492 , H01L29/6659 , H01L29/66659
摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

3. 发明申请

US20150318029A1 Integrated Circuits with Asymmetric and Stacked Transistors 审中-公开
标题翻译：具有不对称和堆叠晶体管的集成电路
公开(公告)号：US20150318029A1
公开(公告)日：2015-11-05
申请号：US14268183
申请日：2014-05-02
申请人： Altera Corporation
发明人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
IPC分类号： G11C7/10 , G11C5/06
CPC分类号： H01L27/1104 , G11C5/06 , G11C7/1051 , G11C11/412 , H01L21/26586 , H01L21/266 , H01L21/82345 , H01L29/1045 , H01L29/4983 , H01L29/66492 , H01L29/6659 , H01L29/66659
摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.
摘要翻译：不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。两个晶体管的栅极也连接在一起。两个晶体管可以具有不同的阈值电压。位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。不对称晶体管也可用于存储器单元中以减少泄漏。

4. 发明授权

US09461161B1 Memory element circuitry with minimum oxide definition width 有权
标题翻译：具有最小氧化物定义宽度的存储元件电路
公开(公告)号：US09461161B1
公开(公告)日：2016-10-04
申请号：US14165103
申请日：2014-01-27
申请人： Altera Corporation
发明人： Jun Liu , Qi Xiang
IPC分类号： G11C11/00 , H01L29/78
CPC分类号： H01L29/78 , G11C11/412
摘要： Integrated circuits with memory circuitry are provided. The memory circuitry may include memory cell transistors and associated pass transistors. The memory cell transistors and the pass transistors may be formed using multiple strips of oxide definition (OD) regions coupled in parallel. The multiple OD strips may have reduced widths. The ratio of the distance from adjacent OD strips to a given OD strip to the width of the given OD strip may be at least 0.5. Forming memory circuitry transistors using this multi-strip arrangement may provide increased levels of stress that improve transistor performance. Each OD strip may have a reduced width that still satisfies fabrication design rules. Forming OD regions having reduced width allows the pass transistors to be overdriven at higher voltage levels to further improve transistor performance.
摘要翻译：提供了具有存储器电路的集成电路。存储器电路可以包括存储器单元晶体管和相关联的传输晶体管。存储单元晶体管和传输晶体管可以使用并联耦合的多个氧化物定义（OD）区段形成。多个OD条可以具有减小的宽度。从相邻OD条到给定OD条的距离与给定OD条的宽度的比可以至少为0.5。使用这种多条布置形成存储器电路晶体管可以提供提高晶体管性能的增加的应力水平。每个OD条可以具有仍然满足制造设计规则的减小的宽度。形成具有减小的宽度的OD区域允许传输晶体管在更高的电压电平下被过载驱动以进一步提高晶体管的性能。

5. 发明授权

US08975928B1 Input-output buffer circuitry with increased drive strength 有权
标题翻译：具有增加驱动强度的输入输出缓冲电路
公开(公告)号：US08975928B1
公开(公告)日：2015-03-10
申请号：US13871931
申请日：2013-04-26
申请人： Altera Corporation
发明人： Jun Liu , Yanzhong Xu
IPC分类号： H03K3/00 , H03K17/10
CPC分类号： H03K19/0185
摘要： Input-output (IO) buffer circuitry is provided that is operable to drive signals off an integrated circuit. The input-output circuitry may include an input-output driver having an asymmetric transistor and/or a low-threshold voltage transistor. The asymmetric transistor may include a first source-drain region at a first dopant concentration level and a second source-drain region at a second dopant concentration level. The first dopant concentration level and the second dopant concentration level may be different. The IO buffer circuitry may be able to prevent issues with regards to hot carrier injection when driving signals with elevated voltages. The IO buffer circuit may also be manufactured without increasing the overall cost.
摘要翻译：提供了可用于从集成电路驱动信号的输入输出（IO）缓冲电路。输入 - 输出电路可以包括具有不对称晶体管和/或低阈值电压晶体管的输入 - 输出驱动器。不对称晶体管可以包括处于第一掺杂剂浓度级的第一源极 - 漏极区域和处于第二掺杂剂浓度水平的第二源极 - 漏极区域。第一掺杂剂浓度水平和第二掺杂剂浓度水平可以不同。当使用升高的电压驱动信号时，IO缓冲器电路可能能够防止关于热载流子注入的问题。也可以在不增加总体成本的情况下制造IO缓冲电路。

6. 发明授权

US09496268B2 Integrated circuits with asymmetric and stacked transistors 有权
公开(公告)号：US09496268B2
公开(公告)日：2016-11-15
申请号：US14268183
申请日：2014-05-02
申请人： Altera Corporation
发明人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
IPC分类号： G11C11/412 , H01L27/11 , G11C7/10 , G11C5/06 , H01L21/8234
CPC分类号： H01L27/1104 , G11C5/06 , G11C7/1051 , G11C11/412 , H01L21/26586 , H01L21/266 , H01L21/82345 , H01L29/1045 , H01L29/4983 , H01L29/66492 , H01L29/6659 , H01L29/66659
摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

7. 发明授权

US09385718B1 Input-output buffer circuit with a gate bias generator 有权
标题翻译：具有栅极偏置发生器的输入输出缓冲电路
公开(公告)号：US09385718B1
公开(公告)日：2016-07-05
申请号：US14058117
申请日：2013-10-18
申请人： Altera Corporation
发明人： Jun Liu , Yanzhong Xu , Bonnie I. Wang , Jeffrey T. Watt
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/017
CPC分类号： H03K19/017509 , H03K19/0005 , H03K19/0013 , H03K19/01721
摘要： An integrated circuit is disclosed. The integrated circuit includes an input-output (IO) buffer circuit. The IO buffer circuit further includes first and second transistors coupled in series. The first transistor receives an input signal and the second transistor receives a pulsed voltage signal. Furthermore, a method to operate the IO buffer circuit is also disclosed.
摘要翻译：公开了一种集成电路。集成电路包括输入输出（IO）缓冲电路。 IO缓冲电路还包括串联耦合的第一和第二晶体管。第一晶体管接收输入信号，第二晶体管接收脉冲电压信号。此外，还公开了一种操作IO缓冲电路的方法。

8. 发明授权

US09190332B1 Method of fabricating integrated circuit transistors with multipart gate conductors 有权
标题翻译：使用多部分栅极导体制造集成电路晶体管的方法
公开(公告)号：US09190332B1
公开(公告)日：2015-11-17
申请号：US14185484
申请日：2014-02-20
申请人： Altera Corporation
发明人： Jun Liu , Albert Ratnakumar , Qi Xiang , Jeffrey Xiaoqi Tung
IPC分类号： H01L21/336 , H01L21/02 , H01L21/8238 , H01L29/66 , H01L21/28 , H01L29/78 , H01L29/49
CPC分类号： H01L21/823842 , H01L21/28 , H01L21/28061 , H01L29/49 , H01L29/4983 , H01L29/66477 , H01L29/66545 , H01L29/7831 , H01L29/7833
摘要： Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.
摘要翻译：提供了金属氧化物半导体晶体管。可以在半导体衬底上形成金属氧化物半导体晶体管。源极和漏极区可以形成在衬底中。可以在源极和漏极区域之间形成诸如高K电介质的栅极绝缘体。栅极可以由多个栅极导体形成。栅极导体可以是具有不同功函数的金属。栅极导体中的第一个可以形成与电介质间隔物相邻的一对边缘栅极导体。边缘栅极导体之间的开口可以用第二栅极导体填充以形成中心栅极导体。可以在制造金属氧化物半导体晶体管中使用自对准栅极形成工艺。

9. 发明授权

US09165640B1 Method of using a PMOS pass gate 有权
标题翻译：使用PMOS通孔的方法
公开(公告)号：US09165640B1
公开(公告)日：2015-10-20
申请号：US14333871
申请日：2014-07-17
申请人： Altera Corporation
发明人： Jun Liu , Albert Ratnakumar , Irfan Rahim , Qi Xiang
IPC分类号： G11C11/00 , G11C11/412
CPC分类号： G11C11/412 , H03K2217/0054
摘要： A method that includes using a PMOS pass gate to couple a first line to a second line, where a gate terminal of the PMOS pass gate is coupled to an output terminal of a memory cell, is described. In one implementation, the PMOS pass gate has a negative threshold voltage. In one implementation, the first line and the second line are respectively first and second interconnect lines of an IC.
摘要翻译：描述了一种方法，其包括使用PMOS传输门将第一行耦合到第二行，其中PMOS传输门的栅极端子耦合到存储器单元的输出端子。在一个实现中，PMOS通道栅极具有负阈值电压。在一个实现中，第一行和第二行分别是IC的第一和第二互连线。

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