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1. 发明授权

US09330218B1 Integrated circuits having input-output circuits with dedicated memory controller circuitry 有权
标题翻译：具有具有专用存储器控制器电路的输入 - 输出电路的集成电路
公开(公告)号：US09330218B1
公开(公告)日：2016-05-03
申请号：US14473978
申请日：2014-08-29
申请人： Altera Corporation
发明人： Gordon Raymond Chiu , Sean Shau-Tu Lu , Warren Trent Nordyke , Bonnie I. Wang , Weizhong Xu
IPC分类号： G11C5/06 , G06F17/50 , G11C7/10 , G11C7/22
CPC分类号： G11C29/022 , G11C5/04 , G11C29/023 , G11C29/028
摘要： An integrated circuit such as a programmable integrated circuit may include input-output circuits each having respective memory controller circuitry. The memory controller circuitry of the input-output circuits may be electrically coupled via a backbone path and configured to collectively form a memory controller. Each memory controller circuitry may include a protocol control circuit and input-output lanes. Memory access requests from on-chip circuitry may be provided to only a selected input-output circuit. The protocol control circuit of the selected input-output circuit may receive the memory access requests and generate memory control signals and local control signals from the memory access requests. The memory control signals may be provided to external memory. The local control signals may be provided to input-output circuits over the backbone path and synchronize the input-output circuits in conveying data between the integrated circuit and the external memory.
摘要翻译：诸如可编程集成电路的集成电路可以包括各自具有各自的存储器控制器电路的输入 - 输出电路。输入 - 输出电路的存储器控制器电路可以经由主干路径电耦合并且被配置为共同形成存储器控制器。每个存储器控制器电路可以包括协议控制电路和输入 - 输出通道。来自片上电路的存储器访问请求可以仅提供给选定的输入 - 输出电路。所选择的输入 - 输出电路的协议控制电路可以接收存储器访问请求，并从存储器访问请求产生存储器控制信号和本地控制信号。存储器控制信号可以被提供给外部存储器。本地控制信号可以通过主干路径被提供给输入 - 输出电路，并使得输入 - 输出电路在集成电路和外部存储器之间传送数据的同步。

2. 发明授权

US09342402B1 Memory interface with hybrid error detection circuitry for modular designs 有权
标题翻译：具有用于模块化设计的混合错误检测电路的存储器接口
公开(公告)号：US09342402B1
公开(公告)日：2016-05-17
申请号：US14166337
申请日：2014-01-28
申请人： Altera Corporation
发明人： Yu Ying Ong , Weizhong Xu
IPC分类号： G06F11/10 , G06F13/16 , G06F3/06 , G06F12/00 , G11C16/10 , G11C16/26 , G11C29/04
CPC分类号： G06F11/1056 , G06F3/0658 , G06F3/068 , G06F11/10 , G06F11/1048 , G06F12/00 , G06F13/16 , G06F13/1668 , G06F13/1673 , G06F13/1694 , G11C16/10 , G11C16/26 , G11C2029/0411
摘要： A programmable integrated circuit with memory interface circuitry is provided. The memory interface circuitry may include soft memory interface logic and hard memory interface logic. The soft memory interface logic may be implemented using programmable circuits, whereas the hard memory interface logic may be implemented using non-programmable dedicated circuits. The soft memory interface logic may include error correction code (ECC) encoder and decoder circuits and circuitry for carrying out a read modified write (RMW) operation. The hard memory interface logic may include a write data buffer, a read data buffer, and other circuitry for supporting the RMW operation. The soft memory interface logic is interposed between the hard memory interface logic and the user logic on the programmable integrated circuit.
摘要翻译：提供了一种具有存储器接口电路的可编程集成电路。存储器接口电路可以包括软存储器接口逻辑和硬存储器接口逻辑。软存储器接口逻辑可以使用可编程电路来实现，而硬存储器接口逻辑可以使用非可编程专用电路来实现。软存储器接口逻辑可以包括纠错码（ECC）编码器和用于执行读取修改的写入（RMW）操作的解码器电路和电路。硬存储器接口逻辑可以包括写数据缓冲器，读数据缓冲器和用于支持RMW操作的其它电路。软存储器接口逻辑介于硬存储器接口逻辑和可编程集成电路上的用户逻辑之间。

3. 发明授权

US09805775B1 Integrated circuits with improved memory controllers 有权
公开(公告)号：US09805775B1
公开(公告)日：2017-10-31
申请号：US14075940
申请日：2013-11-08
申请人： Altera Corporation
发明人： Yu Ying Ong , Weizhong Xu
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G06F13/1689 , G06F13/1694 , G11C7/109
摘要： An integrated circuit may include a memory controller that interfaces with memory that operates using a memory clock signal having repeating memory clock cycles. The memory controller may include controller circuitry that receives memory access requests and generates corresponding memory commands using a controller clock signal having repeating controller clock cycles. The controller circuitry may partition each controller clock cycle into time slots that are associated with respective memory clock cycles. Each generated memory command may require a corresponding number of memory clock cycles to fulfill using the memory. The controller circuitry may assign a time slot to each memory command while preventing conflicts with previously issued memory commands.

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