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1. 发明授权

US10535536B2 Stiffener package and method of fabricating stiffener package 有权
公开(公告)号：US10535536B2
公开(公告)日：2020-01-14
申请号：US16292909
申请日：2019-03-05
申请人： Amkor Technology, Inc.
发明人： Jin Young Kim , Doo Hyun Park , Seung Jae Lee
IPC分类号： H01L21/48 , H01L23/00 , H01L23/498 , H01L23/48 , H01L21/56 , H01L23/16 , H01L23/31 , H01L25/10
摘要： A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.

2. 发明申请

US20170125264A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20170125264A1
公开(公告)日：2017-05-04
申请号：US15397052
申请日：2017-01-03
申请人： Amkor Technology, Inc.
发明人： Won Chul Do , Doo Hyun Park , Jong Sik Paek , Ji Hun Lee , Seong Min Seo
IPC分类号： H01L21/48 , H01L23/00 , H01L23/498 , H01L21/56 , H01L21/683
CPC分类号： H01L21/4846 , H01L21/481 , H01L21/4853 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L23/04 , H01L23/3128 , H01L23/3135 , H01L23/3675 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0655 , H01L2221/68345 , H01L2221/68381 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/81191 , H01L2224/814 , H01L2224/81801 , H01L2224/83005 , H01L2224/92125 , H01L2924/05042 , H01L2924/05442 , H01L2924/10253 , H01L2924/15311 , H01L2924/16251 , H01L2924/1816 , H01L2924/18161 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2924/00014
摘要： Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer.

3. 发明申请

US20170005070A1 Method of manufacturing a semiconductor package 有权
标题翻译：半导体封装的制造方法
公开(公告)号：US20170005070A1
公开(公告)日：2017-01-05
申请号：US15240534
申请日：2016-08-18
申请人： Amkor Technology, Inc.
发明人： Michael G. Kelly , David Jon Hiner , Ji Hun Lee , Won Chul Do , Doo Hyun Park , Ronald Huemoeller
IPC分类号： H01L23/00 , H01L21/48 , H01L25/00 , H01L23/498 , H01L23/31 , H01L25/065 , H01L21/56 , H01L21/78
CPC分类号： H01L24/97 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/78 , H01L23/04 , H01L23/3135 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/16 , H01L24/94 , H01L25/0655 , H01L25/50 , H01L2221/68331 , H01L2221/68345 , H01L2221/68381 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/81203 , H01L2224/81815 , H01L2224/83005 , H01L2224/92125 , H01L2224/92225 , H01L2224/97 , H01L2924/1433 , H01L2924/1434 , H01L2924/15311 , H01L2924/157 , H01L2924/15788 , H01L2924/16251 , H01L2924/18161 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2224/81 , H01L2224/83
摘要： Methods for a semiconductor device package formed in a chip-on-wafer last process using thin film adhesives are disclosed and may include bonding a first carrier to a first surface of an interposer in wafer form, forming conductive bumps on a second surface of the interposer, bonding a second carrier to the conductive bumps utilizing a film adhesive, removing the first carrier from the interposer, bonding a semiconductor die to the first surface of the interposer, and encapsulating the die and the first surface of the interposer in an encapsulant material. The second carrier and the film adhesive may be removed from the conductive bumps utilizing a slide-off process. The interposer and encapsulant may be diced into a plurality of interposer and die structures. One of the die and interposer structures may be bonded to a substrate. The die may be bonded to the interposer utilizing a mass reflow process.
摘要翻译：公开了在使用薄膜粘合剂的晶片上最后工艺中形成的半导体器件封装的方法，并且可以包括将第一载体以晶片形式接合到插入件的第一表面，在插入器的第二表面上形成导电凸块利用薄膜粘合剂将第二载体接合到导电凸块上，从插入件移除第一载体，将半导体管芯接合到插入件的第一表面，并将该插入件的管芯和插入件的第一表面封装在密封材料中。可以使用滑脱法从导电凸起去除第二载体和膜粘合剂。插入器和密封剂可以切成多个插入件和管芯结构。芯片和插入件结构中的一个可以结合到基板。可以使用质量回流工艺将管芯结合到插入件。

4. 发明申请

US20160322317A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20160322317A1
公开(公告)日：2016-11-03
申请号：US15207287
申请日：2016-07-11
申请人： Amkor Technology, Inc.
发明人： Jong Sik Paek , Won Chul Do , Doo Hyun Park , Eun Ho Park , Sung Jae Oh
IPC分类号： H01L23/00 , H01L23/498 , H01L23/367 , H01L23/31 , H01L21/48 , H01L21/56
CPC分类号： H01L24/02 , H01L21/4853 , H01L21/4882 , H01L21/563 , H01L21/6835 , H01L21/76805 , H01L23/3157 , H01L23/3185 , H01L23/3675 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/97 , H01L2021/60022 , H01L2221/68345 , H01L2221/68381 , H01L2224/0231 , H01L2224/0233 , H01L2224/02331 , H01L2224/02372 , H01L2224/02377 , H01L2224/0239 , H01L2224/024 , H01L2224/0401 , H01L2224/05024 , H01L2224/05144 , H01L2224/05155 , H01L2224/13006 , H01L2224/13024 , H01L2224/13026 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/2929 , H01L2224/29299 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/81193 , H01L2924/01013 , H01L2924/01029 , H01L2924/05042 , H01L2924/05442 , H01L2924/12042 , H01L2924/15311 , H01L2924/15788 , H01L2924/16152 , H01L2924/164 , H01L2924/19105 , H01L2924/00 , H01L2924/00014 , H01L2924/014
摘要： A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

5. 发明申请

US20160197032A1 SEMICONDUCTOR DEVICE WITH REDISTRIBUTION LAYERS ON PARTIAL ENCAPSULATION AND NON-PHOTOSENSITIVE PASSIVATION LAYERS 有权
标题翻译：具有重新分配层的半导体器件部分封装和非感光钝化层
公开(公告)号：US20160197032A1
公开(公告)日：2016-07-07
申请号：US15069895
申请日：2016-03-14
申请人： Amkor Technology, Inc.
发明人： Jong Sik Paek , Jin Young Kim , YoonJoo Kim , Jin Han Kim , SeungJae Lee , Se Woong Cha , SungKyu Kim , Jae Hun Bae , Dong Jin Kim , Doo Hyun Park
IPC分类号： H01L23/498 , H01L23/31
CPC分类号： H01L23/49838 , H01L21/568 , H01L23/3114 , H01L23/3128 , H01L23/3185 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02317 , H01L2224/02372 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05568 , H01L2224/0557 , H01L2224/12105 , H01L2224/13014 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2924/12042 , H01L2924/18162 , H01L2924/014 , H01L2924/01082 , H01L2924/01079 , H01L2924/0103 , H01L2924/01083 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/01047 , H01L2924/01029
摘要： A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include a semiconductor die having a first surface, a second surface opposite to the first surface, and side surfaces between the first and second surfaces; an encapsulant encapsulating the side surfaces of the semiconductor die; a contact pad on the first surface of the semiconductor die; and a redistribution layer coupled to the contact pad The redistribution layer may include a linear portion and a circular pad, and a hemispherical conductive bump on the circular pad may include a protruding part extending toward the linear portion and having a radius less than the hemispherical conductive bump. The second surface of the semiconductor die may be coplanar with a surface of the encapsulant. A dielectric layer may cover a portion of the first surface of the semiconductor die and a first surface of the encapsulant.
摘要翻译：公开了一种在部分封装上具有再分配层的半导体器件，并且可以包括具有第一表面，与第一表面相对的第二表面以及第一和第二表面之间的侧表面的半导体管芯; 封装半导体管芯的侧表面的密封剂; 在所述半导体管芯的第一表面上的接触焊盘; 以及耦合到接触焊盘的再分布层。再分配层可以包括直线部分和圆形焊盘，并且圆形焊盘上的半球形导电凸块可以包括朝向线性部分延伸并且具有小于半球形导电性的半径的突出部分磕碰。半导体管芯的第二表面可以与密封剂的表面共面。电介质层可以覆盖半导体管芯的第一表面的一部分和密封剂的第一表面。

6. 发明授权

US09214434B1 Fan-out semiconductor package 有权
标题翻译：扇出半导体封装
公开(公告)号：US09214434B1
公开(公告)日：2015-12-15
申请号：US14017802
申请日：2013-09-04
申请人： Amkor Technology, Inc.
发明人： Jin Young Kim , Doo Hyun Park , Seung Jae Lee
IPC分类号： H01L23/48 , H01L23/28 , H01L23/00
CPC分类号： H01L24/02 , H01L23/16 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/03 , H01L24/19 , H01L24/20 , H01L24/73 , H01L24/81 , H01L25/105 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1035 , H01L2225/1058 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.
摘要翻译：晶片级风扇输出封装包括具有第一表面，第二表面和第三表面的半导体管芯。加强件设置在半导体管芯的第三表面上。导电通孔穿过加强件。电连接到导电通孔的第一和第二导电图案设置在半导体管芯和加强件的第一和第二表面上。焊球电连接到第一或第二导电图案。

7. 发明申请

US20150221601A1 SEMICONDUCTOR DEVICE WITH REDISTRIBUTION LAYERS FORMED UTILIZING DUMMY SUBSTRATES 审中-公开
标题翻译：具有重新分配层的半导体器件形成使用的DUMMY衬底
公开(公告)号：US20150221601A1
公开(公告)日：2015-08-06
申请号：US14449654
申请日：2014-08-01
申请人： Amkor Technology, Inc.
发明人： Jin Young Kim , Ji Young Chung , Doo Hyun Park , Choon Heung Lee
IPC分类号： H01L23/00 , H01L23/31 , H01L21/56
摘要： A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.
摘要翻译：公开了一种使用虚拟衬底形成的具有再分配层的半导体器件，其可以包括在第一虚拟衬底上形成第一再分配层，在第二虚设衬底上形成第二再分布层，将半导体管芯电连接到第一再分配层，电连接第一再分配层到第二再分配层，并且去除虚设基板。第一再分布层可以利用导电柱电连接到第二再分配层。可以在第一和第二再分配层之间形成密封剂材料。第一和第二再分布层之一的侧面部分可以用密封剂覆盖。半导体管芯的表面可以与第二再分配层接触。虚拟基板可以是面板形式。虚拟基板中的一个可以是面板形式，另一个是单元形式。

8. 发明申请

US20150221586A1 SEMICONDUCTOR DEVICE WITH REDUCED THICKNESS 有权
标题翻译：具有减小厚度的半导体器件
公开(公告)号：US20150221586A1
公开(公告)日：2015-08-06
申请号：US14524443
申请日：2014-10-27
申请人： Amkor Technology, Inc.
发明人： Jong Sik Paek , Doo Hyun Park
IPC分类号： H01L23/498 , H01L25/07 , H01L25/00 , H01L23/00
CPC分类号： H01L23/49816 , H01L21/568 , H01L23/3128 , H01L24/17 , H01L24/24 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L25/074 , H01L25/50 , H01L2224/16237 , H01L2224/24101 , H01L2224/24146 , H01L2224/2612 , H01L2224/291 , H01L2224/32135 , H01L2224/32145 , H01L2224/32225 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/49 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/81005 , H01L2224/81203 , H01L2224/82106 , H01L2224/83005 , H01L2224/85 , H01L2224/85005 , H01L2224/85203 , H01L2224/92125 , H01L2224/92225 , H01L2224/92244 , H01L2224/92247 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06558 , H01L2225/06562 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H05K3/4661 , H01L2224/82 , H01L2224/32245 , H01L2224/48247
摘要： A semiconductor device with reduced thickness is disclosed and may include forming a back end of line (BEOL) comprising a redistribution layer on a dummy substrate. A first semiconductor die may be bonded to a first surface of the BEOL and a second semiconductor die may be bonded to the first semiconductor die. The first and second semiconductor dies may be electrically coupled to the BEOL. The first and second semiconductor dies and the BEOL may be encapsulated utilizing a first encapsulant. The dummy substrate may be removed thereby exposing a second surface of the BEOL opposite to the first surface. A solder ball may be placed on the exposed second surface of the BEOL. The second semiconductor may be stacked stepwise on the first semiconductor and may be flip-chip bonded. The semiconductor dies may be electrically coupled to the BEOL utilizing a lateral plating layer or conductive wires.
摘要翻译：公开了一种具有减小厚度的半导体器件，并且可以包括在虚设衬底上形成包括再分配层的线路后端（BEOL）。第一半导体管芯可以结合到BEOL的第一表面上，并且第二半导体管芯可以结合到第一半导体管芯。第一和第二半导体管芯可以电耦合到BEOL。可以利用第一密封剂来封装第一和第二半导体管芯和BEOL。可以去除虚设衬底，从而暴露与第一表面相对的BEOL的第二表面。焊球可以放置在BEOL的暴露的第二表面上。第二半导体可以逐层堆叠在第一半导体上，并且可以倒装芯片接合。半导体管芯可以使用横向镀层或导电线电耦合到BEOL。

9. 发明申请

US20150041980A1 Semiconductor Package with Reduced Thickness 审中-公开
标题翻译：具有降低厚度的半导体封装
公开(公告)号：US20150041980A1
公开(公告)日：2015-02-12
申请号：US14452933
申请日：2014-08-06
申请人： Amkor Technology, Inc.
发明人： Seo Yeon Ahn , Pil Je Sung , Doo Hyun Park , Jong Sik Paek , Young Rae Kim , Hui Tae Kim , Yong Song , Seok Woo Yun
IPC分类号： H01L23/00 , H01L21/304
CPC分类号： H01L24/97 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/3128 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/17 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/03 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68331 , H01L2224/0231 , H01L2224/02311 , H01L2224/02331 , H01L2224/02372 , H01L2224/0239 , H01L2224/03002 , H01L2224/0401 , H01L2224/05083 , H01L2224/05084 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05569 , H01L2224/0557 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2224/06181 , H01L2224/13006 , H01L2224/13111 , H01L2224/13116 , H01L2224/16145 , H01L2224/16146 , H01L2224/17181 , H01L2224/32145 , H01L2224/73204 , H01L2224/7565 , H01L2224/80815 , H01L2224/81005 , H01L2224/81191 , H01L2224/81203 , H01L2224/81207 , H01L2224/81211 , H01L2224/81815 , H01L2224/83005 , H01L2224/831 , H01L2224/83191 , H01L2224/83203 , H01L2224/8385 , H01L2224/92 , H01L2224/92242 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/12042 , H01L2924/18161 , H01L2224/83 , H01L2224/81 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2924/01079 , H01L2924/01028 , H01L2924/0105 , H01L2924/01082 , H01L2924/01083 , H01L2924/0103 , H01L2224/11 , H01L2924/01022 , H01L2924/01074 , H01L2221/683 , H01L21/304 , H01L2224/03 , H01L21/56 , H01L2221/68381 , H01L21/78 , H01L2924/00
摘要： A method for forming a reduced thickness semiconductor package is disclosed and may include providing a first die with an active layer, a through-silicon via (TSV), and a pattern and an under bump metal (UBM) in a dielectric layer on the active layer. A carrier may be bonded to the dielectric layer and the UBM. The first die may be thinned to expose the TSV. A bump pad may be formed on the exposed TSV and a second die may be bonded to the bump pad. The first die, the second die, and an outer surface of the dielectric layer may be encapsulated utilizing a first encapsulant. The carrier may be removed from the dielectric layer and the UBM, and a solder ball may be formed on the UBM. A groove may be formed through the dielectric layer and into the first die.
摘要翻译：公开了一种用于形成厚度减小的半导体封装的方法，并且可以包括提供具有有源层的第一管芯，穿硅通孔（TSV）以及在活性层上的介电层中的图案和下凸块金属（UBM）层。载体可以结合到电介质层和UBM上。第一个模具可能会变薄以暴露TSV。凸起焊盘可以形成在暴露的TSV上，并且第二裸片可以结合到凸块焊盘。可以使用第一密封剂来封装第一裸片，第二裸片和电介质层的外表面。载体可以从电介质层和UBM去除，并且可以在UBM上形成焊球。可以通过介电层形成凹槽并进入第一模具。

10. 发明申请

US20150021751A1 SEMICONDUCTOR DEVICE WITH PLATED PILLARS AND LEADS 有权
标题翻译：具有支柱和导线的半导体器件
公开(公告)号：US20150021751A1
公开(公告)日：2015-01-22
申请号：US14063853
申请日：2013-10-25
申请人： Amkor Technology, Inc.
发明人： Jong Sik Paek , Doo Hyun Park , Seong Min Seo
IPC分类号： H01L23/495 , H01L23/00 , H01L23/498
CPC分类号： H01L24/81 , H01L21/4825 , H01L21/561 , H01L23/3107 , H01L23/49517 , H01L23/49548 , H01L23/49582 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/13147 , H01L2224/16245 , H01L2224/81191 , H01L2224/81447 , H01L2224/8192 , H01L2224/97 , H01L2924/00014 , H01L2224/81
摘要： A semiconductor device with plated pillars and leads is disclosed and may include a semiconductor die comprising a conductive pillar, a conductive lead electrically coupled to the conductive pillar, a metal plating layer covering the conductive lead and conductive pillar, and an encapsulant material encapsulating the semiconductor die and at least a portion of the plating layer. The pillar, lead, and plating layer may comprise copper, for example. The plating layer may fill a gap between the pillar and the lead. A portion of the metal plating layer may, for example, comprise an external lead. The metal plating layer may cover a side surface of the pillar and a top surface, side surface, and at least a portion of a bottom surface of the lead. The metal plating layer may cover side and bottom surfaces of the pillar and top, side, and at least a portion of bottom surfaces of the conductive lead.
摘要翻译：公开了具有镀覆柱和引线的半导体器件，并且可以包括半导体管芯，其包括导电柱，与导电柱电耦合的导电引线，覆盖导电引线和导电柱的金属镀层以及封装半导体的密封材料模具和镀层的至少一部分。例如，柱，铅和镀层可以包括铜。电镀层可以填充柱和引线之间的间隙。金属镀层的一部分可以例如包括外部引线。金属镀层可以覆盖柱的侧表面和顶表面，侧表面以及铅的底表面的至少一部分。金属镀层可以覆盖导电引线的支柱和顶部，侧面和底表面的至少一部分的侧表面和底表面。

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