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1. 发明授权

US11579649B1 Apparatus and methods for clock duty cycle correction and deskew 有权
公开(公告)号：US11579649B1
公开(公告)日：2023-02-14
申请号：US17646638
申请日：2021-12-30
申请人： Analog Devices, Inc.
发明人： Wei-Hung Chen
IPC分类号： G06F1/10 , H03K3/012 , H03K3/017
摘要： Apparatus and methods for clock duty cycle correction and deskew are provided. In certain embodiments, a clock distribution circuit includes a clock driver that provides a differential clock signal to a clock slicer over a pair of transmission lines. The clock distribution circuit further includes a resistor-inductor-capacitor (RLC) tuning circuit for providing termination between the pair of transmission lines and a differential input to the clock slicer. The RLC tuning circuit includes a pair of resistor digital-to-analog converters (resistor DACs or RDACs) coupled to the pair of transmission lines and a pair of controllable inductor-capacitor (LC) circuits coupled to the pair of transmission lines.

2. 发明申请

US20230115318A1 APPARATUS AND METHODS FOR HIGH-SPEED DRIVERS 有权
公开(公告)号：US20230115318A1
公开(公告)日：2023-04-13
申请号：US17450585
申请日：2021-10-12
申请人： Analog Devices, Inc.
发明人： Wei-Hung Chen
IPC分类号： G06F13/42
摘要： Apparatus and methods for high-speed drivers are provided herein. In certain embodiments, a high-speed driver multiplexes two or more data streams. The high-speed driver is implemented with a mux-then-driver topology that provides multiplexing in a predriver circuit. Thus, the multiplexer is eliminated from the full rate output path to relax timing. Driver amplitude control schemes are also disclosed in which a controllable driver includes a group of differential series source transistor (SST) driver slices that are connected in parallel with one another to drive a pair of output terminals, and a group of attenuator slices that are connected in parallel with one another across the pair of output terminals. Additionally, the controllable driver includes a control circuit that activates an attenuator slice for each SST driver slice that is decommissioned to provide output amplitude control.

3. 发明授权

US11640367B1 Apparatus and methods for high-speed drivers 有权
公开(公告)号：US11640367B1
公开(公告)日：2023-05-02
申请号：US17450585
申请日：2021-10-12
申请人： Analog Devices, Inc.
发明人： Wei-Hung Chen
IPC分类号： G06F13/42
摘要： Apparatus and methods for high-speed drivers are provided herein. In certain embodiments, a high-speed driver multiplexes two or more data streams. The high-speed driver is implemented with a mux-then-driver topology that provides multiplexing in a predriver circuit. Thus, the multiplexer is eliminated from the full rate output path to relax timing. Driver amplitude control schemes are also disclosed in which a controllable driver includes a group of differential series source transistor (SST) driver slices that are connected in parallel with one another to drive a pair of output terminals, and a group of attenuator slices that are connected in parallel with one another across the pair of output terminals. Additionally, the controllable driver includes a control circuit that activates an attenuator slice for each SST driver slice that is decommissioned to provide output amplitude control.

4. 发明申请

US20140086364A1 APPARATUS AND METHODS FOR QUADRATURE CLOCK SIGNAL GENERATION 有权
标题翻译：用于时钟信号产生的装置和方法
公开(公告)号：US20140086364A1
公开(公告)日：2014-03-27
申请号：US13629170
申请日：2012-09-27
申请人： ANALOG DEVICES, INC.
发明人： Robert Schell , John Kenney , Wei-Hung Chen
IPC分类号： H04B1/06 , H04B1/16 , H04L27/06
CPC分类号： H03H7/06 , H03B27/00 , H03H7/20 , H03H7/21 , H03H11/22 , H03H2007/0192 , H04L7/0025 , H04L7/033
摘要： Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, a quadrature clock signal generator includes a sine-shaping filter and a polyphase filter. The sine-shaping filter can receive an input clock signal such as a square or rectangular wave and can filter the input clock signal to generate a sinusoidal clock signal. Additionally, the polyphase filter can use the sinusoidal clock signal to generate in-phase (I) and quadrature-phase (Q) clock signals, which can have a phase difference of about ninety degrees. In certain configurations, the in-phase and quadrature-phase clock signals generated by the polyphase filter can be buffered by a buffer circuit to generate in-phase and quadrature-phase sinusoidal reference clock signals suitable for use in a clock and data recover (CDR) system.
摘要翻译：提供了正交时钟信号生成的装置和方法。在某些实现中，正交时钟信号发生器包括正弦整形滤波器和多相滤波器。正弦整形滤波器可以接收诸如正方形或矩形波的输入时钟信号，并且可以对输入时钟信号进行滤波以产生正弦时钟信号。此外，多相滤波器可以使用正弦时钟信号来产生可以具有大约九十度的相位差的同相（I）和正交相（Q）时钟信号。在某些配置中，由多相滤波器产生的同相和正交相位时钟信号可由缓冲电路缓冲，以产生适合在时钟和数据恢复中使用的同相和正交相位正弦参考时钟信号（CDR ）系统。

5. 发明授权

US08760209B2 Apparatus and methods for quadrature clock signal generation 有权
标题翻译：用于正交时钟信号产生的装置和方法
公开(公告)号：US08760209B2
公开(公告)日：2014-06-24
申请号：US13629170
申请日：2012-09-27
申请人： Analog Devices, Inc.
发明人： Robert Schell , John Kenney , Wei-Hung Chen
IPC分类号： H03K3/00 , H03H11/16 , H03K5/13
CPC分类号： H03H7/06 , H03B27/00 , H03H7/20 , H03H7/21 , H03H11/22 , H03H2007/0192 , H04L7/0025 , H04L7/033
摘要： Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, a quadrature clock signal generator includes a sine-shaping filter and a polyphase filter. The sine-shaping filter can receive an input clock signal such as a square or rectangular wave and can filter the input clock signal to generate a sinusoidal clock signal. Additionally, the polyphase filter can use the sinusoidal clock signal to generate in-phase (I) and quadrature-phase (Q) clock signals, which can have a phase difference of about ninety degrees. In certain configurations, the in-phase and quadrature-phase clock signals generated by the polyphase filter can be buffered by a buffer circuit to generate in-phase and quadrature-phase sinusoidal reference clock signals suitable for use in a clock and data recover (CDR) system.
摘要翻译：提供了正交时钟信号生成的装置和方法。在某些实现中，正交时钟信号发生器包括正弦整形滤波器和多相滤波器。正弦整形滤波器可以接收诸如正方形或矩形波的输入时钟信号，并且可以对输入时钟信号进行滤波以产生正弦时钟信号。此外，多相滤波器可以使用正弦时钟信号来产生可以具有大约九十度的相位差的同相（I）和正交相（Q）时钟信号。在某些配置中，由多相滤波器产生的同相和正交相位时钟信号可由缓冲电路缓冲，以产生适合在时钟和数据恢复中使用的同相和正交相位正弦参考时钟信号（CDR ）系统。

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