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1. 发明授权

US09009660B1 Programming in a multiprocessor environment 有权
标题翻译：在多处理器环境中编程
公开(公告)号：US09009660B1
公开(公告)日：2015-04-14
申请号：US11564723
申请日：2006-11-29
申请人： Patrick Robert Griffin , Walter Lee , Anant Agarwal , David Wentzlaff
发明人： Patrick Robert Griffin , Walter Lee , Anant Agarwal , David Wentzlaff
IPC分类号： G06F9/44 , G06F9/45 , G06F9/48
CPC分类号： G06F8/445 , G06F8/30 , G06F8/314 , G06F8/41 , G06F8/427 , G06F8/437 , G06F8/447 , G06F8/451 , G06F8/453 , G06F9/48 , G06F9/546 , G06F2209/548
摘要： Programming in a multiprocessor environment includes accepting a program specification that defines a plurality of processing modules and one or more channels for sending data between ports of the modules, mapping each of the processing modules to run on a set of one or more processing engines of a network of interconnected processing engines, and for at least some of the channels, assigning one or more elements of one or more processing engines in the network to the channel for sending data between respective processing modules.
摘要翻译：在多处理器环境中的编程包括接受定义多个处理模块的程序规范和用于在模块的端口之间发送数据的一个或多个通道，将每个处理模块映射到一组一个或多个处理引擎上互联处理引擎的网络，以及至少一些信道，将网络中的一个或多个处理引擎的一个或多个元素分配给用于在各个处理模块之间发送数据的信道。

2. 发明授权

US08127111B1 Managing data provided to switches in a parallel processing environment 有权
标题翻译：在并行处理环境中管理提供给交换机的数据
公开(公告)号：US08127111B1
公开(公告)日：2012-02-28
申请号：US12110956
申请日：2008-04-28
申请人： David Wentzlaff , Anant Agarwal
发明人： David Wentzlaff , Anant Agarwal
IPC分类号： G06F15/00
CPC分类号： G06F15/16
摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, and coupling circuitry configured to couple data resulting from processing an instruction from at least one of the streams of instructions to the storage module and to the switch.
摘要翻译：集成电路包括多个瓦片。每个瓦片包括包括存储模块的处理器，其中所述处理器被配置为处理多个指令流，开关包括切换电路，以将从其他瓦片到数据路径接收的数据转发到处理器，以及转发其他瓦片从处理器接收的数据到其他瓦片的切换器，以及耦合电路，其被配置为将从指令流中的至少一个处理指令得到的数据耦合到存储模块和交换机。

3. 发明授权

US08190855B1 Coupling data for interrupt processing in a parallel processing environment 有权
标题翻译：在并行处理环境中耦合中断处理数据
公开(公告)号：US08190855B1
公开(公告)日：2012-05-29
申请号：US12036918
申请日：2008-02-25
申请人： Carl G. Ramey , David Wentzlaff , Anant Agarwal
发明人： Carl G. Ramey , David Wentzlaff , Anant Agarwal
IPC分类号： G06F15/00
CPC分类号： G06F9/3885 , G06F9/30003 , G06F9/34 , G06F9/3824 , G06F9/3853 , G06F15/17381 , G06F15/8023 , H04L49/101 , H04L49/109 , H04L49/251
摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further comprises one or more interface modules including circuitry to transfer data to and from a device external to the tiles; and a sub-port routing network including circuitry to route data between a port of a switch and a plurality of sub-ports coupled to one or more interface modules.
摘要翻译：集成电路包括多个瓦片。每个瓦片包括处理器和开关，其包括切换电路，用于将通过数据路径从其他瓦片接收的数据转发到处理器，并转换到其他瓦片，以及将从处理器接收的数据转发到其他瓦片的切换。集成电路还包括一个或多个接口模块，其包括用于将数据传送到和从外部的设备传输到数据块的电路; 以及子端口路由网络，其包括用于在交换机的端口与耦合到一个或多个接口模块的多个子端口之间路由数据的电路。

4. 发明授权

US08046563B1 Virtual architectures in a parallel processing environment 有权
标题翻译：虚拟架构在并行处理环境中
公开(公告)号：US08046563B1
公开(公告)日：2011-10-25
申请号：US12128083
申请日：2008-05-28
申请人： Anant Agarwal , David Wentzlaff
发明人： Anant Agarwal , David Wentzlaff
IPC分类号： G06F15/00 , G06F15/76 , G06F9/455
CPC分类号： G06F15/76 , G06F8/52 , G06F9/30174 , G06F9/30189 , G06F9/3828 , G06F9/3836 , G06F9/3897 , G06F9/455 , G06F9/45504 , G06F9/5061 , G06F15/7867 , G06F2209/5011
摘要： An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing instructions; and reconfiguring the number of processor cores assigned to at least one of the sets during execution based on characteristics associated with executing the instructions.
摘要翻译：集成电路包括多个处理器核。集成电路中的处理指令包括：管理多组处理器核，每组包括分配给与执行指令相关联的功能的一个或多个处理器核; 以及基于与执行指令相关联的特性，在执行期间重新配置分配给至少一个集合的处理器核心的数量。

5. 发明授权

US07734895B1 Configuring sets of processor cores for processing instructions 有权
标题翻译：配置处理器核心集，用于处理指令
公开(公告)号：US07734895B1
公开(公告)日：2010-06-08
申请号：US11414421
申请日：2006-04-28
申请人： Anant Agarwal , David Wentzlaff
发明人： Anant Agarwal , David Wentzlaff
IPC分类号： G06F15/00
CPC分类号： G06F15/76 , G06F8/52 , G06F9/30174 , G06F9/30189 , G06F9/3828 , G06F9/3836 , G06F9/3897 , G06F9/455 , G06F9/45504 , G06F9/5061 , G06F15/7867 , G06F2209/5011
摘要： An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing instructions; and reconfiguring the number of processor cores assigned to at least one of the sets during execution based on characteristics associated with executing the instructions.
摘要翻译：集成电路包括多个处理器核。集成电路中的处理指令包括：管理多组处理器核，每组包括分配给与执行指令相关联的功能的一个或多个处理器核; 以及基于与执行指令相关联的特性，在执行期间重新配置分配给至少一个集合的处理器核心的数量。

6. 发明授权

US08200901B1 Managing cache memory in a parallel processing environment 有权
标题翻译：在并行处理环境中管理高速缓存
公开(公告)号：US08200901B1
公开(公告)日：2012-06-12
申请号：US12983368
申请日：2011-01-03
申请人： David Wentzlaff , Matthew Mattina , Anant Agarwal
发明人： David Wentzlaff , Matthew Mattina , Anant Agarwal
IPC分类号： G06F12/08
CPC分类号： G06F13/24 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/1027 , G06F12/1045 , G06F13/16 , G06F13/4022 , G06F2212/60 , G06F2212/621 , G06F2212/682 , H04L49/109
摘要： An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.
摘要翻译：一种装置包括多个处理器核心，每个处理器核心包括计算单元和存储器。该装置还包括互连网络以在处理器核心之间传送数据。至少一些存储器被配置为处理器核心外部的存储器的高速缓存，并且至少一些处理器核心被配置为通过互连网络传送消息以访问另一处理器核心的高速缓存。

7. 发明授权

US07882307B1 Managing cache memory in a parallel processing environment 有权
标题翻译：在并行处理环境中管理高速缓存
公开(公告)号：US07882307B1
公开(公告)日：2011-02-01
申请号：US11404641
申请日：2006-04-14
申请人： David Wentzlaff , Matthew Mattina , Anant Agarwal
发明人： David Wentzlaff , Matthew Mattina , Anant Agarwal
IPC分类号： G06F12/08
CPC分类号： G06F13/24 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/1027 , G06F12/1045 , G06F13/16 , G06F13/4022 , G06F2212/60 , G06F2212/621 , G06F2212/682 , H04L49/109
摘要： An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.
摘要翻译：一种装置包括多个处理器核心，每个处理器核心包括计算单元和存储器。该装置还包括互连网络以在处理器核心之间传送数据。至少一些存储器被配置为处理器核心外部的存储器的高速缓存，并且至少一些处理器核心被配置为通过互连网络传送消息以访问另一处理器核心的高速缓存。

8. 发明授权

US07793074B1 Directing data in a parallel processing environment 有权
标题翻译：在并行处理环境中指导数据
公开(公告)号：US07793074B1
公开(公告)日：2010-09-07
申请号：US11404281
申请日：2006-04-14
申请人： David Wentzlaff , Anant Agarwal
发明人： David Wentzlaff , Anant Agarwal
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/3885 , G06F9/3828 , G06F9/3851 , G06F15/8007
摘要： An apparatus comprises a plurality of processor cores, and an interconnection network to route data among the processor cores based on destination information in the data. The processor cores are configured to forward the data to a final destination if the destination information indicates that a destination processor core has been reached, or to forward the data to other processor cores if the destination information indicates that a destination processor core has not been reached. The final destination is one of a plurality of destinations indicated by the destination information, the destinations including a plurality of portions of the destination processor core.
摘要翻译：一种装置包括多个处理器核，以及基于数据中的目的地信息在处理器核之间路由数据的互连网络。如果目的地信息指示已经到达目的地处理器核心，则将处理器核心配置为将数据转发到最终目的地，或者如果目的地信息指示目的地处理器核心未到达，则将数据转发到其他处理器核心。最终目的地是由目的地信息指示的多个目的地之一，目的地包括目的处理器核心的多个部分。

9. 发明授权

US07636835B1 Coupling data in a parallel processing environment 有权
标题翻译：在并行处理环境中耦合数据
公开(公告)号：US07636835B1
公开(公告)日：2009-12-22
申请号：US11404658
申请日：2006-04-14
申请人： Carl G. Ramey , David Wentzlaff , Anant Agarwal
发明人： Carl G. Ramey , David Wentzlaff , Anant Agarwal
IPC分类号： G06F15/00
CPC分类号： G06F9/3885 , G06F9/30003 , G06F9/34 , G06F9/3824 , G06F9/3853 , G06F15/17381 , G06F15/8023 , H04L49/101 , H04L49/109 , H04L49/251
摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further comprises one or more interface modules including circuitry to transfer data to and from a device external to the tiles; and a sub-port routing network including circuitry to route data between a port of a switch and a plurality of sub-ports coupled to one or more interface modules.
摘要翻译：集成电路包括多个瓦片。每个瓦片包括处理器和开关，其包括切换电路，用于将通过数据路径从其他瓦片接收的数据转发到处理器，并转换到其他瓦片，以及将从处理器接收的数据转发到其他瓦片的切换。集成电路还包括一个或多个接口模块，其包括用于将数据传送到和从外部的设备传输到数据块的电路; 以及子端口路由网络，其包括用于在交换机的端口与耦合到一个或多个接口模块的多个子端口之间路由数据的电路。

10. 发明授权

US07624248B1 Managing memory in a parallel processing environment 有权
标题翻译：在并行处理环境中管理内存
公开(公告)号：US07624248B1
公开(公告)日：2009-11-24
申请号：US11404187
申请日：2006-04-14
申请人： David Wentzlaff , Anant Agarwal
发明人： David Wentzlaff , Anant Agarwal
IPC分类号： G06F12/06
CPC分类号： G06F13/4022
摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises: a processor, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, according to a switch instruction indicating an input port to which each of multiple output ports of the switch is to be coupled, and a translation lookaside buffer coupled to the switch to translate virtual memory addresses of switch instructions to physical memory addresses of the switch instructions.
摘要翻译：集成电路包括多个瓦片。每个瓦片包括：处理器，开关，其包括切换电路，用于将通过数据路径从其他瓦片接收的数据转发到处理器，以及将其他瓦片的切换转发，并且根据切换将从处理器接收的数据转发到其他瓦片的切换指示要耦合交换机的多个输出端口中的每个输入端口的输入端口以及耦合到开关的转换后备缓冲器，以将开关指令的虚拟存储器地址转换为开关指令的物理存储器地址。

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