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1. 发明授权

US07886293B2 Optimizing system behavior in a virtual machine environment 有权
标题翻译：优化虚拟机环境中的系统行为
公开(公告)号：US07886293B2
公开(公告)日：2011-02-08
申请号：US10886422
申请日：2004-07-07
申请人： Andrew V. Anderson , Steven M. Bennett , Erik C. Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kägi , Michael A. Goldsmith , Sebastian Schoenberg , Richard Uhlig
发明人： Andrew V. Anderson , Steven M. Bennett , Erik C. Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kägi , Michael A. Goldsmith , Sebastian Schoenberg , Richard Uhlig
IPC分类号： G06F9/455
CPC分类号： G06F9/45533 , G06F11/0712 , G06F11/0766
摘要： In one embodiment, the present invention includes a method of transitioning control to guest software in a virtual machine from a virtual machine monitor, receiving control following a transition from the virtual machine to the virtual machine monitor upon an event, and determining whether to modify a state of the guest code, a state of the virtual machine monitor or a state of controls. If such a determination is made, the state may be modified and control is transitioned back to the guest software.
摘要翻译：在一个实施例中，本发明包括一种从虚拟机监视器向虚拟机中的客户软件转换控制的方法，在事件之后从虚拟机向虚拟机监视器转换后接收控制，并且确定是否修改客户代码的状态，虚拟机监视的状态或控制状态。如果做出这样的决定，则可以修改状态并将控制转换回客户软件。

2. 发明授权

US08819699B2 Controlling virtual machines based on performance counters 有权
标题翻译：基于性能计数器控制虚拟机
公开(公告)号：US08819699B2
公开(公告)日：2014-08-26
申请号：US11618446
申请日：2006-12-29
申请人： Erik C. Cota-Robles , Steven M. Bennett , Andrew V. Anderson , Sebastian Schoenberg
发明人： Erik C. Cota-Robles , Steven M. Bennett , Andrew V. Anderson , Sebastian Schoenberg
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： G06F9/45558 , G06F2009/45566
摘要： Embodiments of apparatuses, methods, and systems for controlling virtual machines based on performance counters are disclosed. In one embodiment, an apparatus includes an event counter, a comparator, and virtualization control logic. The event counter is to keep an event count based on the number of occurrences of an event. The comparator is to determine whether the event count has reached a threshold value. The virtualization control logic is to transfer control of the apparatus from a guest to a host in response to the comparator determining that the event count has reached the threshold value.
摘要翻译：公开了用于基于性能计数器来控制虚拟机的设备，方法和系统的实施例。在一个实施例中，装置包括事件计数器，比较器和虚拟化控制逻辑。事件计数器是根据事件的发生次数来保持事件计数。比较器是确定事件计数是否达到阈值。响应于比较器确定事件计数已经达到阈值，虚拟化控制逻辑是将设备从客户机的控制传送到主机。

3. 发明授权

US08286162B2 Delivering interrupts directly to a virtual processor 有权
标题翻译：将中断直接传递到虚拟处理器
公开(公告)号：US08286162B2
公开(公告)日：2012-10-09
申请号：US11323114
申请日：2005-12-30
申请人： Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard A. Uhlig , Udo Steinberg , Sebastian Schoenberg , Sridhar Muthrasanallur , Steven M. Bennett , Andrew V. Anderson , Erik C. Cota-Robles
发明人： Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard A. Uhlig , Udo Steinberg , Sebastian Schoenberg , Sridhar Muthrasanallur , Steven M. Bennett , Andrew V. Anderson , Erik C. Cota-Robles
IPC分类号： G06F9/445 , G06F9/46 , G06F13/24 , G06F13/26 , G06F3/00 , G06F13/00
CPC分类号： G06F13/24 , G06F9/45533 , G06F9/4812
摘要： Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
摘要翻译：公开了用于向虚拟处理器递送中断的装置，方法和系统的实施例。在一个实施例中，装置包括用于接收中断请求，传递逻辑和退出逻辑的接口。交付逻辑是基于中断请求的属性来确定中断请求是否被传送到虚拟处理器。如果传递逻辑确定中断请求不被传送到虚拟处理器，则出口逻辑是将控制传送到主机。

4. 发明授权

US08938737B2 Delivering interrupts directly to a virtual processor 有权
标题翻译：将中断直接传递到虚拟处理器
公开(公告)号：US08938737B2
公开(公告)日：2015-01-20
申请号：US13605412
申请日：2012-09-06
申请人： Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard A. Uhlig , Udo Steinberg , Sebastian Schoenberg , Sridhar Muthrasanallur , Steven M. Bennett , Andrew V. Anderson , Erik C. Cota-Robles
发明人： Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard A. Uhlig , Udo Steinberg , Sebastian Schoenberg , Sridhar Muthrasanallur , Steven M. Bennett , Andrew V. Anderson , Erik C. Cota-Robles
IPC分类号： G06F9/455 , G06F13/24 , G06F13/26 , G06F9/48
CPC分类号： G06F13/24 , G06F9/45533 , G06F9/4812
摘要： Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
摘要翻译：公开了用于向虚拟处理器递送中断的装置，方法和系统的实施例。在一个实施例中，装置包括用于接收中断请求，传递逻辑和退出逻辑的接口。交付逻辑是基于中断请求的属性来确定中断请求是否被传送到虚拟处理器。如果传递逻辑确定中断请求不被传送到虚拟处理器，则出口逻辑是将控制传送到主机。

5. 发明申请

US20120331467A1 Delivering Interrupts Directly To A Virtual Processor 审中-公开
标题翻译：直接向虚拟处理器提供中断
公开(公告)号：US20120331467A1
公开(公告)日：2012-12-27
申请号：US13605412
申请日：2012-09-06
申请人： Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard A. Uhlig , Udo Steinberg , Sebastian Schoenberg , Sridhar Muthrasanallur , Steven M. Bennett , Andrew V. Anderson , Erik C. Cota-Robles
发明人： Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard A. Uhlig , Udo Steinberg , Sebastian Schoenberg , Sridhar Muthrasanallur , Steven M. Bennett , Andrew V. Anderson , Erik C. Cota-Robles
IPC分类号： G06F9/455
CPC分类号： G06F13/24 , G06F9/45533 , G06F9/4812
摘要： Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
摘要翻译：公开了用于向虚拟处理器递送中断的装置，方法和系统的实施例。在一个实施例中，装置包括用于接收中断请求，传递逻辑和退出逻辑的接口。交付逻辑是基于中断请求的属性来确定中断请求是否被传送到虚拟处理器。如果传递逻辑确定中断请求不被传送到虚拟处理器，则出口逻辑是将控制传送到主机。

6. 发明申请

US20080163254A1 CONTROLLING VIRTUAL MACHINES BASED ON PERFORMANCE COUNTERS 有权
标题翻译：基于性能计数器控制虚拟机
公开(公告)号：US20080163254A1
公开(公告)日：2008-07-03
申请号：US11618446
申请日：2006-12-29
申请人： Erik C. Cota-Robles , Steven M. Bennett , Andrew V. Anderson , Sebastian Schoenberg
发明人： Erik C. Cota-Robles , Steven M. Bennett , Andrew V. Anderson , Sebastian Schoenberg
IPC分类号： G06F3/00
CPC分类号： G06F9/45558 , G06F2009/45566
摘要： Embodiments of apparatuses, methods, and systems for controlling virtual machines based on performance counters are disclosed. In one embodiment, an apparatus includes an event counter, a comparator, and virtualization control logic. The event counter is to keep an event count based on the number of occurrences of an event. The comparator is to determine whether the event count has reached a threshold value. The virtualization control logic is to transfer control of the apparatus from a guest to a host in response to the comparator determining that the event count has reached the threshold value.
摘要翻译：公开了用于基于性能计数器来控制虚拟机的设备，方法和系统的实施例。在一个实施例中，装置包括事件计数器，比较器和虚拟化控制逻辑。事件计数器是根据事件的发生次数来保持事件计数。比较器是确定事件计数是否达到阈值。响应于比较器确定事件计数已经达到阈值，虚拟化控制逻辑是将设备从客户机的控制传送到主机。

7. 发明授权

US07793286B2 Methods and systems to manage machine state in virtual machine operations 有权
标题翻译：在虚拟机操作中管理机器状态的方法和系统
公开(公告)号：US07793286B2
公开(公告)日：2010-09-07
申请号：US10324591
申请日：2002-12-19
申请人： Steven M. Bennett , Gilbert Neiger , Erik C. Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Richard A. Uhlig
发明人： Steven M. Bennett , Gilbert Neiger , Erik C. Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Richard A. Uhlig
IPC分类号： G06F9/46 , G06F9/455
CPC分类号： G06F9/45558 , G06F2009/4557
摘要： Methods and systems are provided to control transitions between a virtual machine (VM) and Virtual Machine Monitor (VMM). A processor uses state action indicators to load and/or store associated elements of machine state before completing the transition. The state action indicators may be stored in a Virtual Machine Control Structure (VMCS), predetermined, and/or calculated dynamically. In some embodiments, the values loaded can be directly acquired from the VMCS, predetermined and/or calculated dynamically. In some embodiments, the values stored may be acquired directly from machine state, predetermined and/or calculated dynamically.
摘要翻译：提供了方法和系统来控制虚拟机（VM）和虚拟机监视器（VMM）之间的转换。在完成转换之前，处理器使用状态动作指示器来加载和/或存储机器状态的相关元件。状态动作指示符可以存储在虚拟机控制结构（VMCS）中，预定的和/或动态地计算。在一些实施例中，可以从VMCS直接获取加载的值，预先确定和/或动态地计算。在一些实施例中，存储的值可以直接从机器状态获取，预定和/或动态地计算。

8. 发明申请

US20120117300A1 INVALIDATING TRANSLATION LOOKASIDE BUFFER ENTRIES IN A VIRTUAL MACHINE (VM) SYSTEM 有权
标题翻译：在虚拟机（VM）系统中隐藏翻译预览缓冲区入口
公开(公告)号：US20120117300A1
公开(公告)日：2012-05-10
申请号：US12959109
申请日：2010-12-02
申请人： Erik C. Cota-Robles , Andy Glew , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Gilbert Neiger , Richard Uhlig
发明人： Erik C. Cota-Robles , Andy Glew , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Gilbert Neiger , Richard Uhlig
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F9/30076 , G06F12/1036 , G06F2212/151
摘要： One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.
摘要翻译：本发明的一个实施例是使翻译后备缓冲器（TLB）中的条目无效的技术。处理器中的TLB具有多个TLB条目。当执行无效操作时，每个TLB条目与虚拟机扩展（VMX）标签字相关联，指示相关联的TLB条目是否根据处理器模式而无效。处理器模式是虚拟机（VM）中的执行之一，而不是虚拟机中的执行。无效操作属于一个无效的无效操作集合，它由（1）可能为空的操作集合组合，使一组可变数量的TLB条目无效，（2）一组可能的空白操作，使一个TLB无效条目，（3）使多个TLB条目无效的可能的一组操作，（4）启用和禁用虚拟存储器的使用的可能的一组可能的空操作，以及（5）配置物理的可能的一组操作地址大小，页面大小或其他虚拟内存系统行为，以改变物理机器解释TLB条目的方式。

9. 发明授权

US07865670B2 Invalidating translation lookaside buffer entries in a virtual machine (VM) system 有权
标题翻译：使虚拟机（VM）系统中的翻译后备缓冲区条目无效
公开(公告)号：US07865670B2
公开(公告)日：2011-01-04
申请号：US10973678
申请日：2004-10-25
申请人： Erik C. Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Gilbert Neiger , Richard Uhlig
发明人： Erik C. Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Gilbert Neiger , Richard Uhlig
IPC分类号： G06F13/00
CPC分类号： G06F12/1027 , G06F9/30076 , G06F12/1036 , G06F2212/151
摘要： One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.
摘要翻译：本发明的一个实施例是使翻译后备缓冲器（TLB）中的条目无效的技术。处理器中的TLB具有多个TLB条目。当执行无效操作时，每个TLB条目与虚拟机扩展（VMX）标签字相关联，指示相关联的TLB条目是否根据处理器模式而无效。处理器模式是虚拟机（VM）中的执行之一，而不是虚拟机中的执行。无效操作属于一个无效的无效操作集合，它由（1）可能为空的操作集合组合，使一组可变数量的TLB条目无效，（2）一组可能的空白操作，使一个TLB无效条目，（3）使多个TLB条目无效的可能的一组操作，（4）启用和禁用虚拟存储器的使用的可能的一组可能的空操作，以及（5）配置物理的可能的一组操作地址大小，页面大小或其他虚拟内存系统行为，以改变物理机器解释TLB条目的方式。

10. 发明授权

US07797699B2 Method and apparatus for scheduling virtual machine access to shared resources 有权
标题翻译：调度虚拟机访问共享资源的方法和装置
公开(公告)号：US07797699B2
公开(公告)日：2010-09-14
申请号：US10947902
申请日：2004-09-23
申请人： Alain Kagi , Andrew V. Anderson , Steven M. Bennett , Erik C. Cota-Robles , Gregory M. Jablonski
发明人： Alain Kagi , Andrew V. Anderson , Steven M. Bennett , Erik C. Cota-Robles , Gregory M. Jablonski
IPC分类号： G06F9/455 , G06F9/46 , G06F3/00
CPC分类号： G06F9/5011
摘要： A method for managing IO requests from a virtual machine to access IO resources on a physical machine includes determining a request priority associated with an IO request. The IO request is placed in an appropriate queue in response to determining the request priority.
摘要翻译：用于管理来自虚拟机的IO请求以访问物理机器上的IO资源的方法包括确定与IO请求相关联的请求优先级。响应于确定请求优先级，IO请求被放置在适当的队列中。

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