专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08077623B2 Signal routing in processor arrays 有权
标题翻译：处理器阵列中的信号路由
公开(公告)号：US08077623B2
公开(公告)日：2011-12-13
申请号：US12367814
申请日：2009-02-09
申请人： Andrew William George Duller , William Philip Robbins
发明人： Andrew William George Duller , William Philip Robbins
IPC分类号： G01R31/08
CPC分类号： G06F15/17375
摘要： There is provided a method for routing a plurality of signals in a processor array, the processor array comprising a plurality of processor elements interconnected by a network of switches, each signal having a respective source processor element and at least one destination processor element in the processor array, the method comprising (i) identifying a signal from the plurality of unrouted signals to route; (ii) identifying a candidate route from the source processor element to the destination processor element, the candidate route using a first plurality of switches; (iii) evaluating the candidate route by determining whether there are offset values that allow the signal to be routed through the first plurality of switches; and (iv) attempting to route the signal using one of the offset values identified in step (iii).
摘要翻译：提供了一种用于在处理器阵列中路由多个信号的方法，所述处理器阵列包括通过交换机网络互连的多个处理器元件，每个信号具有相应的源处理器元件和处理器中的至少一个目的地处理器元件阵列，所述方法包括（i）识别来自所述多个未路由信号的信号以路由; （ii）识别从所述源处理器元件到所述目的地处理器元件的候选路线，所述候选路线使用第一多个开关; （iii）通过确定是否存在允许信号通过第一多个交换机路由的偏移值来评估候选路线; 以及（iv）使用步骤（iii）中识别的偏移值之一尝试路由信号。

2. 发明授权

US08352955B2 Process placement in a processor array 有权
标题翻译：处理器阵列中的处理放置
公开(公告)号：US08352955B2
公开(公告)日：2013-01-08
申请号：US12368836
申请日：2009-02-10
申请人： Andrew William George Duller
发明人： Andrew William George Duller
IPC分类号： G06F9/455 , G06F9/46
CPC分类号： G06F9/5066
摘要： There is provided a method for placing a plurality of processes onto respective processor elements in a processor array, the method comprising (i) assigning each of the plurality of processes to a respective processor element to generate a first placement; (ii) evaluating a cost function for the first placement to determine an initial value for the cost function, the result of the evaluation of the cost function indicating the suitability of a placement, wherein the cost function comprises a bandwidth utilization of a bus interconnecting the processor elements in the processor array; (iii) reassigning one or more of the processes to respective different ones of the processor elements to generate a second placement; (iv) evaluating the cost function for the second placement to determine a modified value for the cost function; and (v) accepting or rejecting the reassignments of the one or more processes based on a comparison between the modified value and the initial value.
摘要翻译：提供了一种用于将多个处理放置在处理器阵列中的相应处理器元件上的方法，所述方法包括（i）将多个处理中的每一个分配给相应的处理器元件以产生第一布置; （ii）评估用于所述第一放置的成本函数以确定所述成本函数的初始值，所述成本函数的评估结果指示所述成本函数的适用性，其中所述成本函数包括互连所述总线的总线的带宽利用率处理器阵列中的处理器元件; （iii）将一个或多个过程重新分配给相应的不同处理器元件以产生第二放置; （iv）评估第二次放置的成本函数，以确定成本函数的修正值; 和（v）基于修改值和初始值之间的比较接受或拒绝一个或多个过程的重新分配。

3. 发明申请

US20090210881A1 PROCESS PLACEMENT IN A PROCESSOR ARRAY 有权
标题翻译：处理器阵列中的过程放置
公开(公告)号：US20090210881A1
公开(公告)日：2009-08-20
申请号：US12368836
申请日：2009-02-10
申请人： Andrew William George Duller
发明人： Andrew William George Duller
IPC分类号： G06F9/46
CPC分类号： G06F9/5066
摘要： There is provided a method for placing a plurality of processes onto respective processor elements in a processor array, the method comprising (i) assigning each of the plurality of processes to a respective processor element to generate a first placement; (ii) evaluating a cost function for the first placement to determine an initial value for the cost function, the result of the evaluation of the cost function indicating the suitability of a placement, wherein the cost function comprises a bandwidth utilisation of a bus interconnecting the processor elements in the processor array; (iii) reassigning one or more of the processes to respective different ones of the processor elements to generate a second placement; (iv) evaluating the cost function for the second placement to determine a modified value for the cost function; and (v) accepting or rejecting the reassignments of the one or more processes based on a comparison between the modified value and the initial value.
摘要翻译：提供了一种用于将多个处理放置在处理器阵列中的相应处理器元件上的方法，所述方法包括（i）将多个处理中的每一个分配给相应的处理器元件以产生第一布置; （ii）评估用于所述第一放置的成本函数以确定所述成本函数的初始值，所述成本函数的评估结果指示所述成本函数的适用性，其中所述成本函数包括将所述成本函数的互连的总线的带宽利用率处理器阵列中的处理器元件; （iii）将一个或多个过程重新分配给相应的不同处理器元件以产生第二放置; （iv）评估第二次放置的成本函数，以确定成本函数的修正值; 和（v）基于修改值和初始值之间的比较接受或拒绝一个或多个过程的重新分配。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式