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1. 发明申请

US20140100841A1 Testing a Hardware Emulation Model of a Circuit with Software Checker Routines Designed for an RTL Model of the Circuit 审中-公开
标题翻译：使用针对电路RTL模型设计的软件检查程序来测试电路的硬件仿真模型
公开(公告)号：US20140100841A1
公开(公告)日：2014-04-10
申请号：US13647742
申请日：2012-10-09
申请人： APPLE INC.
发明人： Edmond R. Bures , Jeffrey V. Lent , Fritz A. Boehm
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A hardware emulation system may emulate a plurality of cycles of a circuit, and may store state information at each cycle which specifies signal values for one or more signals of the circuit. After the hardware emulation has finished, the state information may be streamed from the memory of the hardware emulation system to a different storage device that is accessible by a computer system that executes one or more software checker routines. The computer system may execute the software checker routines, which may include passing the signal values specified in the state information to the software checker routines on a cycle-by-cycle basis similarly as if the software checker routines were receiving them in real time directly from the hardware emulation system.
摘要翻译：硬件仿真系统可以模拟电路的多个周期，并且可以在每个周期存储指定电路的一个或多个信号的信号值的状态信息。在硬件仿真完成之后，状态信息可以从硬件仿真系统的存储器流传输到由执行一个或多个软件检查程序的计算机系统可访问的不同的存储设备。计算机系统可以执行软件检查程序，其可以包括将状态信息中指定的信号值逐个循环地传递给软件检查程序，类似于软件检查程序直接从硬件仿真系统。

2. 发明申请

US20140089873A1 Automatically Identifying Resettable Flops For Digital Designs 有权
标题翻译：自动识别数字设计的可复位触发器
公开(公告)号：US20140089873A1
公开(公告)日：2014-03-27
申请号：US13627653
申请日：2012-09-26
申请人： APPLE INC.
发明人： Edmond R. Bures , Fritz A. Boehm
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： An automated process identifies which components that retain their state need to be resettable in a design. The design is analyzed to identify components that retain their state and are non-resettable. A set of simulation tests is run on the design, where each test is known to pass when all components that retain their state are reset at reset. The tests are run with a respective logic value (1 or 0) randomly assigned to each non-resettable component at reset, until a test run fails. The failed test is rerun a specified number of times, each time with a different set of randomly assigned logic values provided to non-resettable components at reset. For each run, statistics are logged for each non-resettable component according to the test results and the logic value provided to the non-resettable component. The process determines which non-resettable components need to be resettable according to the statistics.
摘要翻译：自动化过程确定哪些组件保留其状态需要在设计中重置。分析设计以识别保持其状态并且不可重置的组件。在设计上运行一组仿真测试，当所有保持其状态的组件在复位时都被复位时，每个测试都会被传递。测试在复位时随机分配给每个不可复位组件的相应逻辑值（1或0）运行，直到测试运行失败。失败的测试重新运行指定的次数，每次在复位时向不可复位组件提供不同的随机分配逻辑值集合。对于每个运行，根据测试结果和提供给不可重置组件的逻辑值，为每个不可重置组件记录统计信息。该过程根据统计信息确定哪些不可复位组件需要重置。

3. 发明授权

US09448872B2 Hardware state data logger for silicon debug 有权
标题翻译：用于硅调试的硬件状态数据记录器
公开(公告)号：US09448872B2
公开(公告)日：2016-09-20
申请号：US14179191
申请日：2014-02-12
申请人： Apple Inc.
发明人： Ben D. Jarrett , Fritz A. Boehm
IPC分类号： G06F17/50 , G06F11/07 , G01R31/317 , G06F11/22
CPC分类号： G06F11/0778 , G01R31/31705 , G06F11/22 , G06F11/3476 , G06F17/40
摘要： Systems and methods of utilizing a hardware state data logger to debug in silicon. One or more hardware state data loggers are incorporated into a circuit design and fabricated along with the functional units of the circuit into a fabricated chip. When a problem is encountered during testing of the fabricated chip, a hardware state data logger is enabled to capture and store with a final sequence of events that led to the error. The stored data is then extracted from the fabricated chip and used to determine the underlying cause of the failure.
摘要翻译：利用硬件状态数据记录器在硅中进行调试的系统和方法。将一个或多个硬件状态数据记录器结合到电路设计中并与电路的功能单元一起制造成制造的芯片。当在制造的芯片的测试期间遇到问题时，硬件状态数据记录器能够捕获并存储导致错误的最终事件序列。然后从制造的芯片中提取存储的数据，并用于确定故障的根本原因。

4. 发明授权

US08869080B2 Automatically identifying resettable flops for digital designs 有权
标题翻译：自动识别数字设计的可复位触发器
公开(公告)号：US08869080B2
公开(公告)日：2014-10-21
申请号：US13627653
申请日：2012-09-26
申请人： Apple Inc.
发明人： Edmond R. Bures , Fritz A. Boehm
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： An automated process identifies which components that retain their state need to be resettable in a design. The design is analyzed to identify components that retain their state and are non-resettable. A set of simulation tests is run on the design, where each test is known to pass when all components that retain their state are reset at reset. The tests are run with a respective logic value (1 or 0) randomly assigned to each non-resettable component at reset, until a test run fails. The failed test is rerun a specified number of times, each time with a different set of randomly assigned logic values provided to non-resettable components at reset. For each run, statistics are logged for each non-resettable component according to the test results and the logic value provided to the non-resettable component. The process determines which non-resettable components need to be resettable according to the statistics.
摘要翻译：自动化过程确定哪些组件保留其状态需要在设计中重置。分析设计以识别保持其状态并且不可重置的组件。在设计上运行一组仿真测试，当所有保持其状态的组件在复位时都被复位时，每个测试都会被传递。测试在复位时随机分配给每个不可复位组件的相应逻辑值（1或0）运行，直到测试运行失败。失败的测试重新运行指定的次数，每次在复位时向不可复位组件提供不同的随机分配逻辑值集合。对于每个运行，根据测试结果和提供给不可重置组件的逻辑值，为每个不可重置组件记录统计信息。该过程根据统计信息确定哪些不可复位组件需要重置。

5. 发明申请

US20150227410A1 HARDWARE STATE DATA LOGGER FOR SILICON DEBUG 有权
标题翻译：用于硅调制的硬件状态数据记录
公开(公告)号：US20150227410A1
公开(公告)日：2015-08-13
申请号：US14179191
申请日：2014-02-12
申请人： Apple Inc.
发明人： Ben D. Jarrett , Fritz A. Boehm
IPC分类号： G06F11/07 , G01R31/3177
CPC分类号： G06F11/0778 , G01R31/31705 , G06F11/22 , G06F11/3476 , G06F17/40
摘要： Systems and methods of utilizing a hardware state data logger to debug in silicon. One or more hardware state data loggers are incorporated into a circuit design and fabricated along with the functional units of the circuit into a fabricated chip. When a problem is encountered during testing of the fabricated chip, a hardware state data logger is enabled to capture and store with a final sequence of events that led to the error. The stored data is then extracted from the fabricated chip and used to determine the underlying cause of the failure.
摘要翻译：利用硬件状态数据记录器在硅中进行调试的系统和方法。将一个或多个硬件状态数据记录器结合到电路设计中并与电路的功能单元一起制造成制造的芯片。当在制造的芯片的测试期间遇到问题时，硬件状态数据记录器能够捕获并存储导致错误的最终事件序列。然后从制造的芯片中提取存储的数据，并用于确定故障的根本原因。

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