专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20230066236A1 Criticality-Informed Caching Policies 有权
公开(公告)号：US20230066236A1
公开(公告)日：2023-03-02
申请号：US17727020
申请日：2022-04-22
申请人： Apple Inc.
发明人： Tyler J. Huberty , Vivek Venkatraman , Sandeep Gupta , Eric J. Furbish , Srinivasa Rangan Sridharan , Stephan G. Meier
IPC分类号： G06F12/0891 , G06F12/0831 , G06F12/126 , G06F12/02
摘要： A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.

2. 发明授权

US10776521B2 Security techniques based on memory timing characteristics 有权
公开(公告)号：US10776521B2
公开(公告)日：2020-09-15
申请号：US15679031
申请日：2017-08-16
申请人： Apple Inc.
发明人： Jeremie S. Kim , Minesh H. Patel , Stephan G. Meier , Tyler J. Huberty , Onur Mutlu
IPC分类号： G06F21/71 , H04L9/32 , G06F21/44 , G06F21/73 , G06F21/72 , H04L29/06
摘要： Techniques are disclosed for obtaining data using memory timing characteristics. In some embodiments, a physical unclonable function is used to obtain the data. In various embodiments, a computer system programs a timing parameter of a memory accessible by the computer system to a value that is outside of a specified operable range for the timing parameter. In various embodiments, the computer system performs one or more memory operations to a least a portion of the memory and detects a pattern of errors in the portion of the memory. In some embodiments, the computer system generates a response dependent on the pattern of errors. The response may be used to identify the computer system.

3. 发明授权

US09904624B1 Prefetch throttling in a multi-core system 有权
公开(公告)号：US09904624B1
公开(公告)日：2018-02-27
申请号：US15093173
申请日：2016-04-07
申请人： Apple Inc.
发明人： Tyler J. Huberty , Stephan G. Meier , Khubaib Khubaib
IPC分类号： G06F12/00 , G06F12/08 , G06F13/00 , G06F12/0862 , G06F12/0875 , G06F12/0811
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0875 , G06F2212/283 , G06F2212/452 , G06F2212/602
摘要： In an embodiment, a system may include multiple processors and a cache coupled to the processors. Each processor includes a data cache and a prefetch circuit that may be configured to generate prefetch requests. Each processor may also generate memory operations responsive to cache misses in the data cache. Each processor may transmit the prefetch requests and memory operations to the cache. The cache may queue the memory operations and prefetch requests, and may be configured to detect, on a per-processor basis, occupancy in the queue of memory requests and low confidence prefetch requests from the processor. The cache may determine if the per-processor occupancies exceed one or more thresholds, and may generate a throttle control to the processors responsive to the occupancies. In an embodiment, the cache may generate the throttle control responsive to a history of the last N samples of the occupancies.

4. 发明申请

US20210303471A1 Secondary Prefetch Circuit that Reports Coverage to a Primary Prefetch Circuit to Limit Prefetching by Primary Prefetch Circuit 有权
公开(公告)号：US20210303471A1
公开(公告)日：2021-09-30
申请号：US16832893
申请日：2020-03-27
申请人： Apple Inc.
发明人： Stephan G. Meier , Tyler J. Huberty , Nikhil Gupta
IPC分类号： G06F12/0862
摘要： In an embodiment, a processor includes a plurality of prefetch circuits configured to prefetch data into a data cache. A primary prefetch circuit may be configured to generate first prefetch requests in response to a demand access, and may be configured to invoke a second prefetch circuit in response to the demand access. The second prefetch circuit may implement a different prefetch mechanism than the first prefetch circuit. If the second prefetch circuit reaches a threshold confidence level in prefetching for the demand access, the second prefetch circuit may communicate an indication to the primary prefetch circuit. The primary prefetch circuit may reduce a number of prefetch requests generated for the demand access responsive to the communication from the second prefetch circuit.

5. 发明授权

US10402334B1 Prefetch circuit for a processor with pointer optimization 有权
公开(公告)号：US10402334B1
公开(公告)日：2019-09-03
申请号：US15948072
申请日：2018-04-09
申请人： Apple Inc.
发明人： Stephan G. Meier , Mridul Agarwal
IPC分类号： G06F12/00 , G06F12/0862 , G06F9/30
摘要： In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit with features designed to improve prefetching accuracy and/or reduce power consumption. In an embodiment, the prefetch circuit may be configured to detect that pointer reads are occurring (e.g. “pointer chasing.”) The prefetch circuit may be configured to increase the frequency at which prefetch requests are generated for an access map in which pointer read activity is detected, compared to the frequency at which the prefetch requests would be generated in the pointer read activity is not generated. In an embodiment, the prefetch circuit may also detect access maps that are store-only, and may reduce the frequency of prefetches for store only access maps as compared to the frequency of load-only or load/store maps.

6. 发明授权

US10180905B1 Unified prefetch circuit for multi-level caches 有权
公开(公告)号：US10180905B1
公开(公告)日：2019-01-15
申请号：US15093213
申请日：2016-04-07
申请人： Apple Inc.
发明人： Stephan G. Meier , Tyler J. Huberty , Gerard R. Williams, III , Pradeep Kanapathipillai
IPC分类号： G06F12/00 , G06F12/08 , G06F12/0862 , G06F12/0811
摘要： In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit for a multi-level cache system. The access patterns that are matched to the access maps may include prefetches for different cache levels. Centralizing the generation of prefetches into one prefetch circuit may provide better observability and controllability of prefetching at various levels of the cache hierarchy, in an embodiment. Prefetches at different levels may be controlled individually based on the accuracy of those prefetches, in an embodiment. Additionally, in an embodiment, access patterns that are longer that a given threshold may have the granularity of the prefetches change so that more data is prefetched and the prefetches occur farther in advance, in some embodiments.

7. 发明申请

US20180307862A1 SECURITY TECHNIQUES BASED ON MEMORY TIMING CHARACTERISTICS 审中-公开
公开(公告)号：US20180307862A1
公开(公告)日：2018-10-25
申请号：US15679031
申请日：2017-08-16
申请人： Apple Inc.
发明人： Jeremie S. Kim , Minesh H. Patel , Stephan G. Meier , Tyler J. Huberty , Onur Mutlu
IPC分类号： G06F21/71 , H04L9/32 , G06F21/44
摘要： Techniques are disclosed for obtaining data using memory timing characteristics. In some embodiments, a physical unclonable function is used to obtain the data. In various embodiments, a computer system programs a timing parameter of a memory accessible by the computer system to a value that is outside of a specified operable range for the timing parameter. In various embodiments, the computer system performs one or more memory operations to a least a portion of the memory and detects a pattern of errors in the portion of the memory. In some embodiments, the computer system generates a response dependent on the pattern of errors. The response may be used to identify the computer system.

8. 发明授权

US09116817B2 Pointer chasing prediction 有权
标题翻译：指针追逐预测
公开(公告)号：US09116817B2
公开(公告)日：2015-08-25
申请号：US13890716
申请日：2013-05-09
申请人： Apple Inc.
发明人： Stephan G. Meier
IPC分类号： G06F9/38 , G06F12/08 , G06F9/00
CPC分类号： G06F12/0862 , G06F9/00 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F12/0875
摘要： A system and method for efficient scheduling of dependent load instructions. A processor includes both an execution core and a scheduler that issues instructions to the execution core. The execution core includes a load-store unit (LSU). The scheduler determines a first condition is satisfied, wherein the first condition comprises result data for a first load instruction is predicted eligible for LSU-internal forwarding. The scheduler determines a second condition is satisfied, wherein the second condition comprises a second load instruction younger in program order than the first load instruction is dependent on the first load instruction. In response to each of the first condition and the second condition being satisfied, the scheduler can issue the second load instruction earlier than it otherwise would. The LSU internally forwards the received result data from the first load instruction to address generation logic for the second load instruction.
摘要翻译：一种用于有效调度依赖负载指令的系统和方法。处理器包括执行核心和向执行核心发出指令的调度器。执行核心包括一个加载存储单元（LSU）。调度器确定满足第一条件，其中第一条件包括用于第一加载指令的结果数据被预测为符合LSU内部转发的条件。调度器确定满足第二条件，其中第二条件包括程序次序中的第二加载指令比第一加载指令取决于第一加载指令。响应于满足第一条件和第二条件中的每一个，调度器可以比否则发出第二加载指令。 LSU将接收到的结果数据从第一加载指令内部转发到第二加载指令的地址生成逻辑。

9. 发明授权

US09971694B1 Prefetch circuit for a processor with pointer optimization 有权
公开(公告)号：US09971694B1
公开(公告)日：2018-05-15
申请号：US14748833
申请日：2015-06-24
申请人： Apple Inc.
发明人： Stephan G. Meier , Mridul Agarwal
IPC分类号： G06F12/0862 , G06F9/30
CPC分类号： G06F12/0862 , G06F9/383 , G06F2212/602 , G06F2212/6028
摘要： In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit with features designed to improve prefetching accuracy and/or reduce power consumption. In an embodiment, the prefetch circuit may be configured to detect that pointer reads are occurring (e.g. “pointer chasing.”) The prefetch circuit may be configured to increase the frequency at which prefetch requests are generated for an access map in which pointer read activity is detected, compared to the frequency at which the prefetch requests would be generated in the pointer read activity is not generated. In an embodiment, the prefetch circuit may also detect access maps that are store-only, and may reduce the frequency of prefetches for store only access maps as compared to the frequency of load-only or load/store maps.

10. 发明授权

US09710268B2 Reducing latency for pointer chasing loads 有权
公开(公告)号：US09710268B2
公开(公告)日：2017-07-18
申请号：US14264789
申请日：2014-04-29
申请人： Apple Inc.
发明人： Stephan G. Meier , Pradeep Kanapathipillai , Sandeep Gupta
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30043 , G06F9/3826 , G06F9/3834 , G06F9/3861
摘要： Systems, methods, and apparatuses for reducing the load to load/store address latency in an out-of-order processor. When a producer load is detected in the processor pipeline, the processor predicts whether the producer load is going to hit in the store queue. If the producer load is predicted not to hit in the store queue, then a dependent load or store can be issued early. The result data of the producer load is then bypassed forward from the data cache directly to the address generation unit. This result data is then used to generate an address for the dependent load or store, reducing the latency of the dependent load or store by one clock cycle.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式