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1. 发明授权

US08886481B1 Reducing variation in multi-die integrated circuits 有权
标题翻译：减少多芯片集成电路的变化
公开(公告)号：US08886481B1
公开(公告)日：2014-11-11
申请号：US12835184
申请日：2010-07-13
申请人： Arifur Rahman , Michael J. Hart , Venkatesan Murali
发明人： Arifur Rahman , Michael J. Hart , Venkatesan Murali
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/14 , H01L2224/16225 , H01L2924/15311
摘要： A method of reducing variation in multi-die integrated circuits can include, for each of a plurality of dies, determining at least one performance metric and selecting at least two dies for inclusion within a multi-die integrated circuit according to the at least one performance metric. Systems and devices for executing the steps of the method are also described.
摘要翻译：减少多管芯集成电路中的变化的方法可以包括对于多个管芯中的每一个，确定至少一个性能度量并且根据至少一个性能选择至少两个管芯以包括在多管芯集成电路内度量。还描述了用于执行该方法的步骤的系统和设备。

2. 发明申请

US20110215465A1 MULTI-CHIP INTEGRATED CIRCUIT 审中-公开
标题翻译：多芯片集成电路
公开(公告)号：US20110215465A1
公开(公告)日：2011-09-08
申请号：US12716941
申请日：2010-03-03
申请人： Arifur Rahman , Venkatesan Murali
发明人： Arifur Rahman , Venkatesan Murali
IPC分类号： H01L23/538 , H01L21/60
CPC分类号： H01L21/82 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/5389 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/80 , H01L24/82 , H01L24/83 , H01L24/96 , H01L25/0655 , H01L25/16 , H01L25/50 , H01L2221/6834 , H01L2221/68359 , H01L2224/0401 , H01L2224/04105 , H01L2224/08137 , H01L2224/12105 , H01L2224/24101 , H01L2224/24137 , H01L2224/24226 , H01L2224/2902 , H01L2224/29187 , H01L2224/30181 , H01L2224/30183 , H01L2224/32137 , H01L2224/73267 , H01L2224/80006 , H01L2224/80896 , H01L2224/83005 , H01L2224/83896 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2924/01027 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/14 , H01L2924/141 , H01L2924/1431 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/1437 , H01L2924/1438 , H01L2924/1443 , H01L2924/145 , H01L2924/15311 , H01L2924/181 , H01L2224/11 , H01L2224/19 , H01L2224/82 , H01L2924/00 , H01L2224/83
摘要： An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.
摘要翻译：集成电路（IC）将具有第一片上互连结构的第一IC芯片（芯片）和具有第二片上互连结构的第二IC芯片组合在重建的晶片基座上。第二IC芯片与氧化物到氧化物边缘接合边缘接合到第一IC芯片。芯片到芯片的互连结构电耦合第一IC芯片和第二IC芯片。

3. 发明申请

US20140030836A1 Silicon Carbide Lamina 失效
标题翻译：碳化硅薄片
公开(公告)号：US20140030836A1
公开(公告)日：2014-01-30
申请号：US13558843
申请日：2012-07-26
申请人： Venkatesan Murali , Steve Babayan , Christopher J. Petti
发明人： Venkatesan Murali , Steve Babayan , Christopher J. Petti
IPC分类号： H01L33/02 , H01L21/762
CPC分类号： H01L33/0079 , H01L21/76254 , H01L29/2003 , H01L29/66462 , H01L29/7786 , H01L33/007
摘要： A method of fabricating an electronic device includes providing a silicon carbide or diamond-like carbon donor body and implanting ions into a first surface of the donor body to define a cleave plane. After implanting, an epitaxial layer is formed on the first surface, and a temporary carrier is coupled to the epitaxial layer. A lamina is cleaved from the donor body at the cleave plane, and the temporary carrier is removed from the lamina. In some embodiments a light emitting diode or a high electron mobility transistor is fabricated from the lamina and epitaxial layer.
摘要翻译：一种制造电子器件的方法包括提供碳化硅或类金刚石碳供体，并将离子注入施主体的第一表面以限定解理面。在注入之后，在第一表面上形成外延层，并且临时载体耦合到外延层。在切割平面处从供体体中切割薄层，并将临时载体从薄片上移除。在一些实施例中，从层板和外延层制造发光二极管或高电子迁移率晶体管。

4. 发明授权

US08518724B2 Method to form a device by constructing a support element on a thin semiconductor lamina 失效
标题翻译：通过在薄半导体层上构造支撑元件来形成器件的方法
公开(公告)号：US08518724B2
公开(公告)日：2013-08-27
申请号：US13450414
申请日：2012-04-18
申请人： Christopher J. Petti , Mohamed M. Hilali , Theodore Smick , Venkatesan Murali , Kathy J. Jackson , Zhiyong Li , Gopalakrishna Prabhu
发明人： Christopher J. Petti , Mohamed M. Hilali , Theodore Smick , Venkatesan Murali , Kathy J. Jackson , Zhiyong Li , Gopalakrishna Prabhu
IPC分类号： H01L21/00 , H01L31/00
CPC分类号： H01L31/1892 , H01L31/0747 , H01L31/1864 , Y02E10/50
摘要： A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating, or by application of a precursor and curing in situ, resulting in a support element which may be, for example, metal, ceramic, polymer, etc. This is in contrast to pre-formed support element which is affixed to the lamina following its formation, or to a donor wafer from which the lamina is subsequently cleaved.Fabricating the support element in situ may avoid the use of adhesives to attach the lamina to a permanent support element. In some embodiments, this process flow allows the lamina to be annealed at high temperature, then to have an amorphous silicon layer formed on each face of the lamina following that anneal.
摘要翻译：描述了半导体组件，其中在半导体层的表面上构造支撑元件。形成厚度约为50微米或更小的薄层之后，例如通过镀覆或通过施加前体和原位固化来形成支撑元件，得到支撑元件，其可以用于例如，金属，陶瓷，聚合物等。这与预先形成的支撑元件形成对比，该预制形成的支撑元件在其形成之后固定到层板上，或者与施加器晶片相接触，该晶片随后被切割。原位制造支撑元件可以避免使用粘合剂将薄片附着到永久支撑元件上。在一些实施例中，该工艺流程允许薄层在高温下退火，然后在该退火之后具有在层的每个表面上形成的非晶硅层。

5. 发明授权

US06331446B1 Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state 有权
标题翻译：用于将加热到部分凝胶状态的底部填充材料用于底部填充受控崩溃芯片连接（C4）集成电路封装的工艺
公开(公告)号：US06331446B1
公开(公告)日：2001-12-18
申请号：US09261648
申请日：1999-03-03
申请人： Duane Cook , Venkatesan Murali , Suresh Ramalingam , Nagesh Vodrahalli
发明人： Duane Cook , Venkatesan Murali , Suresh Ramalingam , Nagesh Vodrahalli
IPC分类号： H01L2144
CPC分类号： H01L24/31 , H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83951 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01082 , H01L2924/14 , H01L2924/00 , H01L2924/3512 , H01L2224/0401
摘要： A partial gel step in the underfilling of an integrated circuit that is mounted to a substrate. The process involves dispensing a first underfill material and then heating the underfill material to a partial gel state. The partial gel step may reduce void formation and improve adhesion performance during moisture loading.
摘要翻译：在安装到基板上的集成电路的底部填充中的部分凝胶步骤。该方法包括分配第一底部填充材料，然后将底部填充材料加热至部分凝胶状态。部分凝胶步骤可以减少空隙形成并改善湿气加载期间的粘附性能。

6. 发明授权

US06219910B1 Method for cutting integrated circuit dies from a wafer which contains a plurality of solder bumps 有权
标题翻译：用于从包含多个焊料凸块的晶片切割集成电路管芯的方法
公开(公告)号：US06219910B1
公开(公告)日：2001-04-24
申请号：US09263118
申请日：1999-03-05
申请人： Venkatesan Murali
发明人： Venkatesan Murali
IPC分类号： H05K334
CPC分类号： H01L24/11 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , Y10T29/49144 , Y10T29/53178 , H01L2224/05599
摘要： A method for cutting an integrated circuit die from a wafer. The method may include the step of forming a solder bump on an integrated circuit wafer. The solder bump is then oxidized. The oxidization process may form an outer oxidized layer on the solder bump. An integrated circuit die is cut from the wafer after the oxidization step. The cutting process may include spraying a fluid onto the wafer. The oxidized solder may form a protective layer which reduces the amount of particles and lead hydroxide formed during the cutting process. The integrated circuit die may be mounted to a package substrate by reflowing the solder bump onto a pad of the substrate. The outer oxidized layer may be removed with a flux that is used to reflow the solder bump onto the substrate.
摘要翻译：一种用于从晶片切割集成电路管芯的方法。该方法可以包括在集成电路晶片上形成焊料凸块的步骤。焊料凸点然后被氧化。氧化过程可以在焊料凸块上形成外部氧化层。在氧化步骤之后从晶片切割集成电路管芯。切割过程可以包括将流体喷涂到晶片上。氧化的焊料可以形成保护层，其减少在切割过程中形成的颗粒和氢氧化铅的量。集成电路管芯可以通过将焊料凸块回流到衬底的焊盘上而被安装到封装衬底。外部氧化层可以用用于将焊料凸块回流到衬底上的焊剂去除。

7. 发明授权

US08629061B2 Method for three-dimensional packaging of electronic devices 失效
标题翻译：电子设备三维包装方法
公开(公告)号：US08629061B2
公开(公告)日：2014-01-14
申请号：US13490460
申请日：2012-06-07
申请人： Venkatesan Murali , Arvind Chari , Gopal Prabhu
发明人： Venkatesan Murali , Arvind Chari , Gopal Prabhu
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L21/2007 , H01L21/486 , H01L21/6835 , H01L23/147 , H01L23/49827 , H01L2221/68345 , H01L2224/16
摘要： An interposer is fabricated from a lamina. A donor body is provided, ions are implanted into a first surface of the donor body to define a cleave plane, a temporary carrier is separably contacted to the donor body, and the lamina is cleaved from the donor body. The lamina has front surface and a back surface, with a thickness from the front surface to the back surface. A via hole is formed in the lamina, where the via hole extends through the thickness of the lamina. The temporary carrier is removed from the lamina, and the lamina may be fabricated into an interposer for three-dimensional integrated circuit packages.
摘要翻译：插层由薄片制成。提供供体，离子被植入供体体的第一表面以限定劈平面，临时载体与供体本体分离接触，并且层从供体体上切下。薄片具有前表面和后表面，其厚度从前表面到后表面。通孔形成在层板中，通孔延伸穿过层的厚度。将临时载体从薄片上移除，并将薄片制成三维集成电路封装的插入件。

8. 发明申请

US20120258561A1 Low-Temperature Method for Forming Amorphous Semiconductor Layers 审中-公开
标题翻译：用于形成非晶半导体层的低温方法
公开(公告)号：US20120258561A1
公开(公告)日：2012-10-11
申请号：US13083625
申请日：2011-04-11
申请人： Jian Li , Venkatesan Murali , Yonghua Liu , Dong Xu
发明人： Jian Li , Venkatesan Murali , Yonghua Liu , Dong Xu
IPC分类号： H01L31/02 , H01L31/0368 , H01L31/0376
CPC分类号： H01L31/202 , H01L31/056 , H01L31/0747 , H01L31/1804 , H01L31/1896 , Y02E10/52 , Y02E10/547 , Y02P70/521
摘要： In embodiments of the present invention an undoped amorphous, nanocrystalline or microcrystalline semiconductor layer and a heavily doped amorphous, nanocrystalline, or microcrystalline semiconductor layer are formed on a monocrystalline silicon lamina. The lamina is the base region of a photovoltaic cell, while the amorphous, nanocrystalline or monocrystalline layers serve to passivate the surface of the lamina, reducing recombination at this surface. In embodiments, the heavily doped layer additionally serves as either the emitter of the cell or to provide electrical contact to the base layer. The undoped and heavily doped layers are deposited at low temperature, for example about 150 degrees C. or less with hydrogen dilution. This low temperature allows use of low-temperature materials and methods, while increased hydrogen dilution improves film quality and/or conductivity.
摘要翻译：在本发明的实施例中，在单晶硅层上形成未掺杂的非晶，纳米晶体或微晶半导体层和重掺杂的非晶，纳米晶体或微晶半导体层。薄层是光伏电池的基极区域，而非晶态，纳米晶体或单晶层用于钝化层的表面，减少了该表面的复合。在实施例中，重掺杂层另外用作电池的发射极或提供与基极层的电接触。未掺杂的和重掺杂的层在低温下沉积，例如约150℃或更低的氢稀释。这种低温允许使用低温材料和方法，而增加的氢稀释改善了膜质量和/或导电性。

9. 发明申请

US20120220068A1 Method to Form a Device by Constructing a Support Element on a Thin Semiconductor Lamina 失效
标题翻译：通过在薄型半导体层上构造支撑元件来形成器件的方法
公开(公告)号：US20120220068A1
公开(公告)日：2012-08-30
申请号：US13450414
申请日：2012-04-18
申请人： Christopher J. Petti , Mohamed M. Hilali , Theodore Smick , Venkatesan Murali , Kathy J. Jackson , Zhiyong Li , Gopalakrishna Prabhu
发明人： Christopher J. Petti , Mohamed M. Hilali , Theodore Smick , Venkatesan Murali , Kathy J. Jackson , Zhiyong Li , Gopalakrishna Prabhu
IPC分类号： H01L31/0376 , H01L31/18
CPC分类号： H01L31/1892 , H01L31/0747 , H01L31/1864 , Y02E10/50
摘要： A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating, or by application of a precursor and curing in situ, resulting in a support element which may be, for example, metal, ceramic, polymer, etc. This is in contrast to pre-formed support element which is affixed to the lamina following its formation, or to a donor wafer from which the lamina is subsequently cleaved.Fabricating the support element in situ may avoid the use of adhesives to attach the lamina to a permanent support element. In some embodiments, this process flow allows the lamina to be annealed at high temperature, then to have an amorphous silicon layer formed on each face of the lamina following that anneal.
摘要翻译：描述了半导体组件，其中在半导体层的表面上构造支撑元件。形成厚度约为50微米或更小的薄层之后，例如通过镀覆或通过施加前体和原位固化来形成支撑元件，得到支撑元件，其可以用于例如，金属，陶瓷，聚合物等。这与预先形成的支撑元件形成对比，该预制形成的支撑元件在其形成之后固定到层板上，或者与施加器晶片相接触，该晶片随后被切割。原位制造支撑元件可以避免使用粘合剂将薄片附着到永久支撑元件上。在一些实施例中，该工艺流程允许薄层在高温下退火，然后在该退火之后具有在层的每个表面上形成的非晶硅层。

10. 发明授权

US08173452B1 Method to form a device by constructing a support element on a thin semiconductor lamina 有权
标题翻译：通过在薄半导体层上构造支撑元件来形成器件的方法
公开(公告)号：US08173452B1
公开(公告)日：2012-05-08
申请号：US12980424
申请日：2010-12-29
申请人： Christopher J. Petti , Mohamed M. Hilali , Theodore Smick , Venkatesan Murali , Kathy J. Jackson , Zhiyong Li , Gopalakrishna Prabhu
发明人： Christopher J. Petti , Mohamed M. Hilali , Theodore Smick , Venkatesan Murali , Kathy J. Jackson , Zhiyong Li , Gopalakrishna Prabhu
IPC分类号： H01L21/00
CPC分类号： H01L31/1892 , H01L31/0747 , H01L31/1864 , Y02E10/50
摘要： A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating, or by application of a precursor and curing in situ, resulting in a support element which may be, for example, metal, ceramic, polymer, etc. This is in contrast to a rigid or semi-rigid pre-formed support element which is affixed to the lamina following its formation, or to a donor wafer from which the lamina is subsequently cleaved. Fabricating the support element in situ may avoid the use of adhesives to attach the lamina to a permanent support element; such adhesives may be unable to tolerate processing temperatures and conditions required to complete the device. In some embodiments, this process flow allows the lamina to be annealed at high temperature, then to have an amorphous silicon layer formed on each face of the lamina following that anneal. A device may be formed which comprises the lamina, such as a photovoltaic cell.
摘要翻译：描述了半导体组件，其中在半导体层的表面上构造支撑元件。形成厚度约为50微米或更小的薄层之后，例如通过镀覆或通过施加前体和原位固化来形成支撑元件，得到支撑元件，其可以用于例如，金属，陶瓷，聚合物等。这与刚性或半刚性的预成形支撑元件形成对比，该刚性或半刚性的预成型支撑元件在其形成之后固定到层板上，或者与施加器晶片相接触，其中层板随后被切割。原位制造支撑元件可以避免使用粘合剂将薄片附着到永久支撑元件上; 这种粘合剂可能不能容忍完成装置所需的加工温度和条件。在一些实施例中，该工艺流程允许薄层在高温下退火，然后在该退火之后具有在层的每个表面上形成的非晶硅层。可以形成包括层的器件，例如光伏电池。

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