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1. 发明授权

US11537860B2 Neural net work processing 有权
公开(公告)号：US11537860B2
公开(公告)日：2022-12-27
申请号：US16826586
申请日：2020-03-23
申请人： Arm Limited
发明人： Rune Holm , John Wakefield Brothers, III
IPC分类号： G06N3/063 , G06F7/50 , G06F17/18 , G06F7/535 , G06F7/523
摘要： A neural network processor is disclosed that includes a combined convolution and pooling circuit that can perform both convolution and pooling operations. The circuit can perform a convolution operation by a multiply circuit determining products of corresponding input feature map and convolution kernel weight values, and an add circuit accumulating the products determined by the multiply circuit in storage. The circuit can perform an average pooling operation by the add circuit accumulating input feature map data values in the storage, a divisor circuit determining a divisor value, and a division circuit dividing the data value accumulated in the storage by the determined divisor value. The circuit can perform a maximum pooling operation by a maximum circuit determining a maximum value of input feature map data values, and storing the determined maximum value in the storage.

2. 发明申请

US20210133542A1 EXECUTING NEURAL NETWORKS ON ELECTRONIC DEVICES 有权
公开(公告)号：US20210133542A1
公开(公告)日：2021-05-06
申请号：US16670140
申请日：2019-10-31
申请人： Arm Limited
发明人： Rune Holm , John Wakefield Brothers, III
IPC分类号： G06N3/063 , G06N3/04 , G06F17/16 , G06F7/544
摘要： When performing a matrix-vector multiply operation for neural network processing, a set of one or more input vectors to be multiplied by a matrix of data values is scanned to identify data positions of the input vector(s) for which the data value is non-zero in at least one of the input vectors. For each of the data positions identified as having a non-zero value in at least one of the input vectors, the set of data values from the matrix of data values for that data position is fetched from memory and the matrix-vector multiply operation is performed using the data values for the input vectors for the data positions identified as being non-zero and the fetched set(s) of data values from the matrix of data values for those data position(s).

3. 发明授权

US11620503B2 Neural network processing 有权
公开(公告)号：US11620503B2
公开(公告)日：2023-04-04
申请号：US16823063
申请日：2020-03-18
申请人： Arm Limited
发明人： Dominic Hugo Symes , Rune Holm
IPC分类号： G06N3/063 , G06N3/04
摘要： A method for performing neural network processing, and a corresponding data processing system. The data processing system is configured to define one or more tiles for use when reading a portion of an input feature map from memory or writing a portion of an output feature map to memory. The data processing system is also configured to provide information which allows positions falling within the defined one or more tiles to be mapped to memory locations to allow a processor to read data for an input feature map from memory or to write data for a portion of an output feature map to memory.

4. 发明授权

US11334788B2 Neural network including memory elements implemented at nodes 有权
公开(公告)号：US11334788B2
公开(公告)日：2022-05-17
申请号：US16315991
申请日：2017-06-14
申请人： Arm Limited
发明人： Shidhartha Das , Rune Holm
IPC分类号： G06N3/06 , G06N3/04 , G11C11/54 , G06N3/063 , G11C13/00 , G06N3/08
摘要： Broadly speaking, embodiments of the present techniques provide a reconfigurable hardware-based artificial neural network, wherein weights for each neural network node of the artificial neural network are obtained via training performed external to the neural network.

5. 发明授权

US11288066B2 Register-based matrix multiplication with multiple matrices per register 有权
公开(公告)号：US11288066B2
公开(公告)日：2022-03-29
申请号：US16626701
申请日：2018-06-08
申请人： ARM LIMITED
发明人： David Hennah Mansell , Rune Holm , Ian Michael Caulfield , Jelena Milanovic
IPC分类号： G06F9/302 , G06F9/30 , G06F17/16
摘要： Techniques for performing matrix multiplication in a data processing apparatus are disclosed, comprising apparatuses, matrix multiply instructions, methods of operating the apparatuses, and virtual machine implementations. Registers, each register for storing at least four data elements, are referenced by a matrix multiply instruction and in response to the matrix multiply instruction a matrix multiply operation is carried out. First and second matrices of data elements are extracted from first and second source registers, and plural dot product operations, acting on respective rows of the first matrix and respective columns of the second matrix are performed to generate a square matrix of result data elements, which is applied to a destination register. A higher computation density for a given number of register operands is achieved with respect to vector-by-element techniques.

6. 发明申请

US20220092409A1 NEURAL NETWORK PROCESSING 有权
公开(公告)号：US20220092409A1
公开(公告)日：2022-03-24
申请号：US17030176
申请日：2020-09-23
申请人： Arm Limited
发明人： John Wakefield Brothers, III , Rune Holm , Elliott Maurice Simon Rosemarine
IPC分类号： G06N3/08
摘要： To perform neural network processing to modify an input data array to generate a corresponding output data array using a filter comprising an array of weight data, at least one of the input data array and the filter are subdivided into a plurality of portions, a plurality of neural network processing passes using the portions are performed, and the output generated by each processing pass is combined to provide the output data array.

7. 发明申请

US20210295138A1 NEURAL NETWORK PROCESSING 有权
公开(公告)号：US20210295138A1
公开(公告)日：2021-09-23
申请号：US16823063
申请日：2020-03-18
申请人： Arm Limited
发明人： Dominic Hugo Symes , Rune Holm
IPC分类号： G06N3/063 , G06N3/04
摘要： A method for performing neural network processing, and a corresponding data processing system. The data processing system is configured to define one or more tiles for use when reading a portion of an input feature map from memory or writing a portion of an output feature map to memory. The data processing system is also configured to provide information which allows positions falling within the defined one or more tiles to be mapped to memory locations to allow a processor to read data for an input feature map from memory or to write data for a portion of an output feature map to memory.

8. 发明授权

US10528350B2 Shared resources in a data processing apparatus for executing a plurality of threads 有权
公开(公告)号：US10528350B2
公开(公告)日：2020-01-07
申请号：US15505714
申请日：2015-07-28
申请人： ARM LIMITED
发明人： Rune Holm , David Hennah Mansell
IPC分类号： G06F9/30 , G06F9/52
摘要： A data processing apparatus (100) executes threads and includes a general program counter (PC) (120) identifying an instruction to be executed for at least a subset of the threads. Each thread has a thread PC (184). The subset of threads has at least one lock parameter (188, 500-504) for tracking exclusive access to shared resources. In response to a first instruction executed for a thread, the processor (160) modifies the at least one lock parameter (188), (500-504) to indicate that the thread has gained exclusive access to the shared resource. In response to a second instruction, the processor modifies the at least one lock parameter (188, 500-504) to indicate that the thread no longer has exclusive access. A selector (110) selects one of the subset of threads based on the at least one lock parameter (188, 500-504) and sets the general PC (120) to the thread PC (184) of the selected thread.

9. 发明授权

US09037835B1 Data processing method and apparatus for prefetching 有权
标题翻译：预取数据处理方法和装置
公开(公告)号：US09037835B1
公开(公告)日：2015-05-19
申请号：US14061842
申请日：2013-10-24
申请人： ARM LIMITED
发明人： Ganesh Suryanarayan Dasika , Rune Holm
IPC分类号： G06F9/00 , G06F12/08 , G06F15/00
CPC分类号： G06F12/0862 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F2212/6026
摘要： A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.
摘要翻译：数据处理设备包括处理电路20，用于执行对存储器件40的第一地址的第一存储器访问指令和到存储器件40的第二地址的第二存储器访问指令，第一地址不同于第二地址。数据处理装置还包括预取电路30，用于基于步幅长度70和指令分析电路50从存储器装置40预取数据，用于确定第一地址和第二地址之间的差异。还提供跨步精炼电路60以基于步幅长度的因素和由指令分析电路50计算的差异的因素来细化步幅长度。

10. 发明授权

US11494188B2 Prefetch strategy control for parallel execution of threads based on one or more characteristics of a stream of program instructions indicative that a data access instruction within a program is scheduled to be executed a plurality of times 有权
公开(公告)号：US11494188B2
公开(公告)日：2022-11-08
申请号：US14061837
申请日：2013-10-24
申请人： ARM LIMITED
发明人： Ganesh Suryanarayan Dasika , Rune Holm , David Hennah Mansell
IPC分类号： G06F9/345 , G06F9/38
摘要： A single instruction multiple thread (SIMT) processor includes execution circuitry, prefetch circuitry and prefetch strategy selection circuitry. The prefetch strategy selection circuitry serves to detect one or more characteristics of a stream of program instructions that are being executed to identify whether or not a given data access instruction within a program will be executed a plurality of times. The prefetch strategy to use is selected from a plurality of selectable prefetch strategies in dependence upon the detection of such detected characteristics.

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