专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07772059B2 Method for fabricating graphene transistors on a silicon or SOI substrate 有权
标题翻译：在硅或SOI衬底上制造石墨烯晶体管的方法
公开(公告)号：US07772059B2
公开(公告)日：2010-08-10
申请号：US12015358
申请日：2008-01-16
申请人： Ashesh Parikh , Andrew Marshall
发明人： Ashesh Parikh , Andrew Marshall
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/78684 , H01L29/1606 , H01L29/66742 , H01L29/7781
摘要： A method of fabricating graphene transistors, comprising providing an SOI substrate, performing an optional threshold implant on the SOI substrate, forming an upper silicon layer mesa island, carbonizing the silicon layer into SiC utilizing a gaseous source, converting the SiC into graphene, forming source/drain regions on opposite longitudinal ends of the graphene, forming gate oxide between the source/drain regions on the graphene, forming gate material over the gate oxide, creating a transistor edge, depositing dielectric onto the transistor edge and performing back end processing.
摘要翻译：一种制造石墨烯晶体管的方法，包括提供SOI衬底，在SOI衬底上执行可选的阈值注入，形成上硅层台面岛，利用气态碳将硅层碳化为SiC，将SiC转化为石墨烯，形成源 /漏极区域，在石墨烯的源极/漏极区域之间形成栅极氧化物，在栅极氧化物上形成栅极材料，产生晶体管边缘，将电介质沉积到晶体管边缘上并执行后端处理。

2. 发明申请

US20100133512A1 METHOD FOR FABRICATING CARBON NANOTUBE TRANSISTORS ON A SILICON OR SOI SUBSTRATE 有权
标题翻译：在硅或SOI衬底上制备碳纳米管晶体管的方法
公开(公告)号：US20100133512A1
公开(公告)日：2010-06-03
申请号：US12700479
申请日：2010-02-04
申请人： Ashesh Parikh , Andrew Marshall
发明人： Ashesh Parikh , Andrew Marshall
IPC分类号： H01L29/66
CPC分类号： H01L51/055 , B82Y10/00 , H01L51/0002 , H01L51/0048 , H01L51/0541 , Y10S977/842 , Y10S977/845 , Y10S977/938
摘要： A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed.
摘要翻译：公开了一种形成具有受控直径和手性的单层壁厚（SWT）碳纳米管（CNT）晶体管的方法。将光刻定义的单晶硅籽晶层转化为单晶碳化硅种子层。在碳化硅的顶表面上形成单层石墨烯。在存在含碳气体和金属催化剂原子的情况下，从石墨烯层生长SWT CNT晶体管体。在碳化硅种子层的每一端的硅化源极和漏极区域在CNT形成期间提供催化剂金属原子。 SWT CNT的直径由图案种子层的宽度确定。栅极电介质层上的共形淀积栅介质层和晶体管栅极完成了CNT晶体管。还公开了具有多个CNT体，分离栅极和不同直径的CNT晶体管。

3. 发明申请

US20100038627A1 METHOD FOR FABRICATING CARBON NANOTUBE TRANSISTORS ON A SILICON OR SOI SUBSTRATE 有权
公开(公告)号：US20100038627A1
公开(公告)日：2010-02-18
申请号：US12192457
申请日：2008-08-15
申请人： Ashesh Parikh , Andrew Marshall
发明人： Ashesh Parikh , Andrew Marshall
IPC分类号： H01L29/12
CPC分类号： H01L51/055 , B82Y10/00 , H01L51/0002 , H01L51/0048 , H01L51/0541 , Y10S977/842 , Y10S977/845 , Y10S977/938
摘要： A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed.

4. 发明申请

US20090181502A1 METHOD FOR FABRICATING GRAPHENE TRANSISTORS ON A SILICON OR SOI SUBSTRATE 有权
标题翻译：在硅或SOI衬底上制作石墨晶体管的方法
公开(公告)号：US20090181502A1
公开(公告)日：2009-07-16
申请号：US12015358
申请日：2008-01-16
申请人： Ashesh Parikh , Andrew Marshall
发明人： Ashesh Parikh , Andrew Marshall
IPC分类号： H01L21/336
CPC分类号： H01L29/78684 , H01L29/1606 , H01L29/66742 , H01L29/7781
摘要： A method of fabricating graphene transistors, comprising providing an SOI substrate, performing an optional threshold implant on the SOI substrate, forming an upper silicon layer mesa island, carbonizing the silicon layer into SiC utilizing a gaseous source, converting the SiC into graphene, forming source/drain regions on opposite longitudinal ends of the graphene, forming gate oxide between the source/drain regions on the graphene, forming gate material over the gate oxide, creating a transistor edge, depositing dielectric onto the transistor edge and performing back end processing.
摘要翻译：一种制造石墨烯晶体管的方法，包括提供SOI衬底，在SOI衬底上执行可选的阈值注入，形成上硅层台面岛，利用气态碳将硅层碳化为SiC，将SiC转化为石墨烯，形成源 /漏极区域，在石墨烯的源极/漏极区域之间形成栅极氧化物，在栅极氧化物上形成栅极材料，产生晶体管边缘，将电介质沉积到晶体管边缘上并执行后端处理。

5. 发明授权

US07842955B2 Carbon nanotube transistors on a silicon or SOI substrate 有权
标题翻译：硅或SOI衬底上的碳纳米管晶体管
公开(公告)号：US07842955B2
公开(公告)日：2010-11-30
申请号：US12700479
申请日：2010-02-04
申请人： Ashesh Parikh , Andrew Marshall
发明人： Ashesh Parikh , Andrew Marshall
IPC分类号： H01L29/15 , H01L29/76 , H01L29/94
CPC分类号： H01L51/055 , B82Y10/00 , H01L51/0002 , H01L51/0048 , H01L51/0541 , Y10S977/842 , Y10S977/845 , Y10S977/938
摘要： A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed.
摘要翻译：公开了一种形成具有受控直径和手性的单层壁厚（SWT）碳纳米管（CNT）晶体管的方法。将光刻定义的单晶硅籽晶层转化为单晶碳化硅种子层。在碳化硅的顶表面上形成单层石墨烯。在存在含碳气体和金属催化剂原子的情况下，从石墨烯层生长SWT CNT晶体管体。在碳化硅种子层的每一端的硅化源极和漏极区域在CNT形成期间提供催化剂金属原子。 SWT CNT的直径由图案种子层的宽度确定。栅极电介质层上的共形淀积栅介质层和晶体管栅极完成了CNT晶体管。还公开了具有多个CNT体，分离栅极和不同直径的CNT晶体管。

6. 发明授权

US07687308B2 Method for fabricating carbon nanotube transistors on a silicon or SOI substrate 有权
标题翻译：在硅或SOI衬底上制造碳纳米管晶体管的方法
公开(公告)号：US07687308B2
公开(公告)日：2010-03-30
申请号：US12192457
申请日：2008-08-15
申请人： Ashesh Parikh , Andrew Marshall
发明人： Ashesh Parikh , Andrew Marshall
IPC分类号： H01L51/40 , H01L21/336
CPC分类号： H01L51/055 , B82Y10/00 , H01L51/0002 , H01L51/0048 , H01L51/0541 , Y10S977/842 , Y10S977/845 , Y10S977/938
摘要： A method of forming a single wall thickness (SWT) carbon nanotube (CNT) transistor with a controlled diameter and chirality is disclosed. A photolithographically defined single crystal silicon seed layer is converted to a single crystal silicon carbide seed layer. A single layer of graphene is formed on the top surface of the silicon carbide. The SWT CNT transistor body is grown from the graphene layer in the presence of carbon containing gases and metal catalyst atoms. Silicided source and drain regions at each end of the silicon carbide seed layer provide catalyst metal atoms during formation of the CNT. The diameter of the SWT CNT is established by the width of the patterned seed layer. A conformally deposited gate dielectric layer and a transistor gate over the gate dielectric layer complete the CNT transistor. CNT transistors with multiple CNT bodies, split gates and varying diameters are also disclosed.
摘要翻译：公开了一种形成具有受控直径和手性的单层壁厚（SWT）碳纳米管（CNT）晶体管的方法。将光刻定义的单晶硅籽晶层转化为单晶碳化硅种子层。在碳化硅的顶表面上形成单层石墨烯。在存在含碳气体和金属催化剂原子的情况下，从石墨烯层生长SWT CNT晶体管体。在碳化硅种子层的每一端的硅化源极和漏极区域在CNT形成期间提供催化剂金属原子。 SWT CNT的直径由图案种子层的宽度确定。栅极电介质层上的共形淀积的栅介质层和晶体管栅极完成了CNT晶体管。还公开了具有多个CNT体，分离栅极和不同直径的CNT晶体管。

7. 发明申请

US20120105046A1 CURRENT MIRROR USING AMBIPOLAR DEVICES 审中-公开
标题翻译：目前使用环形器件的镜子
公开(公告)号：US20120105046A1
公开(公告)日：2012-05-03
申请号：US12914661
申请日：2010-10-28
申请人： Andrew Marshall , Ashesh Parikh
发明人： Andrew Marshall , Ashesh Parikh
IPC分类号： G05F3/16
CPC分类号： G05F3/262 , H01L29/78684
摘要： Current mirrors have been used in analog electronics with both CMOS and bipolar transistors for many years. Conventional current minor designs, though, may not be suitable for emerging technology transistors, such as graphene transistors, carbon nanotube (CNT) transistors, or other ambipolar transistors. Here, a current minor has been provided that uses ambipolar transistors, which accounts for the more unusual I-V (drain current to gate-source voltage) characteristics of ambipolar transistors.
摘要翻译：多年来，电流镜已被用于具有CMOS和双极晶体管的模拟电子设备中。然而，传统的当前小型设计可能不适用于新兴技术晶体管，例如石墨烯晶体管，碳纳米管（CNT）晶体管或其他双极晶体管。这里，已经提供了使用双极晶体管的当前次要器件，其考虑了双极晶体管的异常I-V（漏极电流到栅极 - 源极电压）特性。

8. 发明授权

US07458058B2 Verifying a process margin of a mask pattern using intermediate stage models 有权
标题翻译：使用中间阶段模型验证掩模图案的过程边缘
公开(公告)号：US07458058B2
公开(公告)日：2008-11-25
申请号：US11150613
申请日：2005-06-10
申请人： Ashesh Parikh , William R. McKee , Thomas J. Aton
发明人： Ashesh Parikh , William R. McKee , Thomas J. Aton
IPC分类号： G06F17/50 , G06F19/00 , G21K5/00 , G03F1/00
CPC分类号： H01L22/20 , G03F1/36 , H01L2924/0002 , H01L2924/00
摘要： Verifying a process margin for a mask pattern includes receiving the mask pattern for patterning features on a semiconductor wafer. The mask pattern is modified according to a wafer pattern model operable to estimate a wafer pattern resulting from the mask pattern. An intermediate stage model is selected to apply to a portion of the mask pattern, where the intermediate stage model is operable to estimate an intermediate stage of the wafer pattern. A process margin of the portion is verified by selecting a test of the intermediate stage model, and performing the test on the portion to verify the process margin of the portion.
摘要翻译：验证掩模图案的处理余量包括接收用于在半导体晶片上构图特征的掩模图案。根据可操作以估计由掩模图案产生的晶片图案的晶片图案模型修改掩模图案。选择中间级模型以应用于掩模图案的一部分，其中中间级模型可操作以估计晶片图案的中间级。通过选择中间阶段模型的测试来验证该部分的处理余量，并对该部分执行测试以验证该部分的处理余量。

9. 发明授权

US08394681B2 Transistor layout for manufacturing process control 有权
标题翻译：用于制造工艺控制的晶体管布局
公开(公告)号：US08394681B2
公开(公告)日：2013-03-12
申请号：US12850813
申请日：2010-08-05
申请人： Ashesh Parikh , Anand Seshadri
发明人： Ashesh Parikh , Anand Seshadri
IPC分类号： H01L21/8234
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.
摘要翻译：公开了对称电路（图4）。电路包括第一晶体管（220），其具有具有锐角的基本形状的平行四边形（图5A）的第一通道。第一晶体管具有沿第一晶体方向（520）取向的第一电流路径（506）。第一控制门（362）覆盖在第一通道上。第二晶体管（222）连接到第一晶体管，并具有具有锐角的平行四边形的基本形状的第二通道。第二晶体管具有平行于第一电流路径定向的第二电流路径（502）。第二控制门（360）覆盖第二通道。

10. 发明申请

US20120117519A1 METHOD OF TRANSISTOR MATCHING 审中-公开
标题翻译：晶体管匹配方法
公开(公告)号：US20120117519A1
公开(公告)日：2012-05-10
申请号：US13288584
申请日：2011-11-03
申请人： Ashesh Parikh
发明人： Ashesh Parikh
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/12 , Y02P90/265
摘要： A method to reduce transistor-to-transistor Ids variation in an integrated circuit by adjusting transistor gate lengths and optionally transistor widths in the design data base prior to the application of OPC and prior to forming a photomask. A method to reduce transistor-to-transistor Ids variation in an integrated circuit by adjusting transistor gate lengths and optionally transistor widths in the design data base prior to the application of OPC and prior to printing a gate pattern and optionally printing an active pattern on a wafer.
摘要翻译：通过在施加OPC之前并且在形成光掩模之前调整晶体管栅极长度和设计数据库中的可选晶体管宽度来减小集成电路中的晶体管至晶体管Ids变化的方法。一种通过在施加OPC之前并且在打印栅极图案之前调整晶体管栅极长度和设计数据库中的晶体管宽度以及可选地将印刷活动图案放置在一个集成电路中以降低晶体管至晶体管Ids变化的方法晶圆。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式