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1. 发明授权

US08813003B2 System and method for inferring higher level descriptions from RTL topology based on naming similarities and dependency 有权
标题翻译：基于命名相似性和依赖性从RTL拓扑推断更高层次的描述的系统和方法
公开(公告)号：US08813003B2
公开(公告)日：2014-08-19
申请号：US14056094
申请日：2013-10-17
申请人： Atrenta, Inc.
发明人： Anshuman Nayak , Samantak Chakrabarti , Brijesh Agrawal , Nitin Bhardwaj
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A system and methods are disclosed for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs. In particular, rule-based interface matching is automatically performed by analyzing actual port names on instances of functional elements and blocks to form signal groupings that comprise a higher-level abstracted description. An example syntax is provided for defining rules that are used to define how various analysis are performed. Data describing standard interfaces on common Intellectual Property (IP) blocks is optionally made available to facilitate interface matching. Also, a facility is included to allow user-guided mapping on instantiated interfaces with respect to actual port names in an RTL-level design.
摘要翻译：公开了用于从注册传输级（RTL）网表推断电路连接的更高级别描述的系统和方法，以便为复杂的片上系统（SOC）设计提供更易于理解和可管理的设计描述。特别地，基于规则的接口匹配通过分析功能元件和块的实例上的实际端口名称来自动执行，以形成包含更高级抽象描述的信号分组。提供了一个示例语法来定义用于定义如何执行各种分析的规则。可选地提供了描述共同知识产权（IP）块的标准接口的数据，以便于接口匹配。此外，还包括一个工具，以便在RTL级别设计中实现与实际端口名称相关的实例化接口上的用户指导映射。

2. 发明申请

US20140282338A1 SYSTEM AND METHOD FOR ALTERING CIRCUIT DESIGN HIERARCHY TO OPTIMIZE ROUTING AND POWER DISTRIBUTION 有权
标题翻译：改进电路设计分级的优化路由和功率分配的系统和方法
公开(公告)号：US20140282338A1
公开(公告)日：2014-09-18
申请号：US13829211
申请日：2013-03-14
申请人： ATRENTA, INC.
发明人： Anshuman Nayak , Samantak Chakrabarti , Brijesh Agrawal , Nilam Sachan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , G06F2217/78 , Y02E40/76 , Y04S10/545
摘要： Systems and methods are disclosed for modifying the hierarchy of a System-on-Chip and other circuit designs to provide better routing and performance as well as more effective power distribution. A user specifies desired modifications to the design hierarchy and then the system automatically alters the hierarchy by performing group, ungroup, and move operations to efficiently and optimally implement the desired hierarchy modifications. Any modifications to port and signal names are automatically resolved by the system and the resultant RTL matches the function of the input RTL. The user then evaluates the revised hierarchy with regard to power distribution and routing congestion, and further hierarchy modifications are performed if necessary. A widget user interface facility is included to allow user-guided direction of hierarchy modifications in an iterative fashion.
摘要翻译：公开了用于修改片上系统和其他电路设计的层次结构以提供更好的路由和性能以及更有效的功率分配的系统和方法。用户指定对设计层次结构的所需修改，然后系统通过执行组，取消组合和移动操作自动更改层次结构，以有效和最佳地实现所需的层次结构修改。对端口和信号名称进行的任何修改都将由系统自动解决，所得到的RTL与输入RTL的功能相匹配。用户然后评估关于功率分配和路由拥塞的修订层级，并且如果需要，执行进一步的层次结构修改。包括小部件用户界面工具，以允许以迭代方式进行层次修改的用户指导方向。

3. 发明申请

US20150379176A1 SYSTEM AND METHOD FOR VIEWING AND MODIFYING CONFIGURABLE RTL MODULES 有权
标题翻译：用于查看和修改可配置RTL模块的系统和方法
公开(公告)号：US20150379176A1
公开(公告)日：2015-12-31
申请号：US14745675
申请日：2015-06-22
申请人： Atrenta, Inc.
发明人： Anshuman Nayak , Samantak Chakrabarti , Nilam Sachan , Nitin Bhardwaj , Brijesh Agrawal , Nishant Sharma
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A configurable module editor and viewer (CMVE) reads the RTL description of a configurable module keeping track of all possible configuration options. Configuration options include pre-processor macros that are normally removed by RTL parsers. The CMVE allows users to view multiple configurations simultaneously. The CMVE assists users in editing the configurable module by presenting a simplified view of interest, while automatically propagating changes and maintaining consistency in the configurable module. The CMVE outputs updated RTL that maintains all configuration options.
摘要翻译：可配置的模块编辑器和查看器（CMVE）读取可配置模块的RTL描述，跟踪所有可能的配置选项。配置选项包括通常由RTL解析器删除的预处理器宏。 CMVE允许用户同时查看多个配置。 CMVE通过呈现感兴趣的简化视图来帮助用户编辑可配置模块，同时自动传播更改并维护可配置模块的一致性。 CMVE输出更新的RTL，维护所有配置选项。

4. 发明授权

US08930863B2 System and method for altering circuit design hierarchy to optimize routing and power distribution using initial RTL-level circuit description netlist 有权
标题翻译：用于改变电路设计层级的系统和方法，以使用初始RTL级电路描述网表优化路由和配电
公开(公告)号：US08930863B2
公开(公告)日：2015-01-06
申请号：US13829211
申请日：2013-03-14
申请人： Atrenta, Inc.
发明人： Anshuman Nayak , Samantak Chakrabarti , Brijesh Agrawal , Nilam Sachan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , G06F2217/78 , Y02E40/76 , Y04S10/545
摘要： Systems and methods are disclosed for modifying the hierarchy of a System-on-Chip and other circuit designs to provide better routing and performance as well as more effective power distribution. A user specifies desired modifications to the design hierarchy and then the system automatically alters the hierarchy by performing group, ungroup, and move operations to efficiently and optimally implement the desired hierarchy modifications. Any modifications to port and signal names are automatically resolved by the system and the resultant RTL matches the function of the input RTL. The user then evaluates the revised hierarchy with regard to power distribution and routing congestion, and further hierarchy modifications are performed if necessary. A widget user interface facility is included to allow user-guided direction of hierarchy modifications in an iterative fashion.
摘要翻译：公开了用于修改片上系统和其他电路设计的层次结构以提供更好的路由和性能以及更有效的功率分配的系统和方法。用户指定对设计层次结构的所需修改，然后系统通过执行组，取消组合和移动操作自动更改层次结构，以有效和最佳地实现所需的层次结构修改。对端口和信号名称进行的任何修改都将由系统自动解决，所得到的RTL与输入RTL的功能相匹配。用户然后评估关于功率分配和路由拥塞的修订层级，并且如果需要，执行进一步的层次结构修改。包括小部件用户界面工具，以允许以迭代方式进行层次修改的用户指导方向。

5. 发明授权

US08782587B2 Systems and methods for generating a higher level description of a circuit design based on connectivity strengths 有权
标题翻译：基于连接强度生成电路设计的更高级别描述的系统和方法
公开(公告)号：US08782587B2
公开(公告)日：2014-07-15
申请号：US13683287
申请日：2012-11-21
申请人： Atrenta, Inc.
发明人： Anshuman Nayak , Samantak Chakrabarti , Brijesh Agrawal , Chandrakanti Vamshi Krishna
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5045
摘要： Provided are systems and methods for generating a higher level description of a circuit design comprising a plurality of interface instances. One or more buckets for each source instance with respect to each destination instance included in the circuit design are generated, and then the one or more buckets are sorted based on a number of bucket entries in each bucket. One or more interface instances are generated based on the sorted buckets. The higher level description of the circuit design is generated based on the one or more interface instances.
摘要翻译：提供了用于生成包括多个接口实例的电路设计的更高级别描述的系统和方法。生成针对包含在电路设计中的每个目的地实例的每个源实例的一个或多个存储桶，然后基于每个存储桶中的桶数目的数量对一个或多个存储桶进行排序。一个或多个接口实例基于排序的桶生成。基于一个或多个接口实例生成电路设计的更高级别的描述。

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