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    • 3. 发明授权
    • Semiconductor device
    • 半导体器件
    • US09035923B2
    • 2015-05-19
    • US13225856
    • 2011-09-06
    • Hajime KimuraAtsushi Umezaki
    • Hajime KimuraAtsushi Umezaki
    • G09G5/00G09G3/36
    • G09G3/3648G09G3/2096G09G3/3677G09G3/3688G09G2300/0426G09G2300/0814G09G2300/0819G09G2320/0209G09G2320/0223G09G2320/043
    • A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.
    • 提供了在选择期间输出到栅极信号线的信号的延迟或失真减小的半导体器件。 半导体器件包括栅极信号线,向栅极信号线输出选择信号和非选择信号的第一和第二栅极驱动器电路,以及电连接到栅极信号线并被提供有两个信号的像素。 在选择栅极信号线的期间,第一和第二栅极驱动电路都将选择信号输出到栅极信号线。 在没有选择栅极信号线的期间,第一和第二栅极驱动电路中的一个将非选择信号输出到栅极信号线,另一个栅极驱动电路既不输出选择信号也不输出非选择信号 信号到门信号线。