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1. 发明授权

US07307879B2 Nonvolatile memory device, and its manufacturing method 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US07307879B2
公开(公告)日：2007-12-11
申请号：US11291048
申请日：2005-11-29
申请人： Atsushi Yokoi , Masao Nakano
发明人： Atsushi Yokoi , Masao Nakano
IPC分类号： G11C16/04 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475 , G11C11/5621 , G11C2211/5611 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/7887 , H01L29/7923
摘要： On a channel region enclosed by a pair of diffusion layers 13A, 13B, a first insulating layer 15, a charge accumulative layer 17, and a second insulating layer 19 are stacked up in this order, and on the second insulating layer 19, two control gate layers 21A, 21B spaced across a gap G1 are disposed in the middle of the channel width direction. The charge accumulative layer 17 has discrete charge traps, and, accordingly, movement of charge in the layer is limited. In the charge accumulative layer 17, the charges injected depend on the writing voltage applied in control gate layers 21A, 21B and can be localized beneath the control gate layers 21A, 21B through which a writing voltage is applied. The presence or absence of charges can be controlled in every charge accumulative region beneath the control gate layers 21A, 21B, so that multi-value storage in the memory cell can be realized.
摘要翻译：在由一对扩散层13A，13B，第一绝缘层15，电荷累积层17和第二绝缘层19围绕的沟道区域上依次层叠，在第二绝缘层19上，在间隙G 1间隔开的两个控制栅极层21A，21B设置在沟道宽度方向的中间。电荷累积层17具有离散的电荷陷阱，因此层中的电荷的移动受到限制。在电荷累积层17中，注入的电荷取决于施加在控制栅极层21A，21B中的写入电压，并且可以位于施加写入电压的控制栅极层21A，21B的下方。可以在控制栅极层21A，21B下方的每个电荷累积区域中控制电荷的存在或不存在，从而可以实现存储单元中的多值存储。

2. 发明授权

US08875105B2 Efficiently developing software using test cases to check the conformity of the software to the requirements 有权
标题翻译：使用测试用例高效开发软件，以检查软件是否符合要求
公开(公告)号：US08875105B2
公开(公告)日：2014-10-28
申请号：US13410000
申请日：2012-03-01
申请人： Atsushi Yokoi
发明人： Atsushi Yokoi
IPC分类号： G06F9/44 , H03M11/00 , G06F11/36
CPC分类号： G06F11/3684 , G06F11/3624
摘要： A method for efficiently developing software and supporting creation of source code so as to develop software that meets the requirements. A plurality of test cases defining a plurality of respective tests to be executed to check the conformity of the software to the requirements are used. In a test execution step, one or more specific test cases selected from the plurality of test cases are executed or the specific test cases are caused to be executed. Furthermore, a test result of a test case executed or caused to be executed in the test case execution step is added to the source code.
摘要翻译：一种有效开发软件并支持创建源代码以开发满足要求的软件的方法。使用定义要执行的多个相应测试的多个测试用例来检查软件与要求的一致性。在测试执行步骤中，执行从多个测试用例中选择的一个或多个特定测试用例，或者使特定测试用例被执行。此外，将在测试用例执行步骤中执行或被执行的测试用例的测试结果添加到源代码中。

3. 发明申请

US20120117545A1 EFFICIENTLY DEVELOPING SOFTWARE USING TEST CASES TO CHECK THE CONFORMITY OF THE SOFTWARE TO THE REQUIREMENTS 有权
标题翻译：使用测试案例检查软件符合要求的有效开发软件
公开(公告)号：US20120117545A1
公开(公告)日：2012-05-10
申请号：US13273478
申请日：2011-10-14
申请人： Atsushi Yokoi
发明人： Atsushi Yokoi
IPC分类号： G06F11/36
CPC分类号： G06F11/3684 , G06F11/3624
摘要： A method, system and computer program product for efficiently developing software and supporting creation of source code so as to develop software that meets the requirements. A plurality of test cases defining a plurality of respective tests to be executed to check the conformity of the software to the requirements are used. In a test execution step, one or more specific test cases selected from the plurality of test cases are executed or the specific test cases are caused to be executed. Furthermore, a test result of a test case executed or caused to be executed in the test case execution step is added to the source code.
摘要翻译：一种方法，系统和计算机程序产品，用于高效开发软件并支持创建源代码，以开发满足要求的软件。使用定义要执行的多个相应测试的多个测试用例来检查软件与要求的一致性。在测试执行步骤中，执行从多个测试用例中选择的一个或多个特定测试用例，或者使特定测试用例被执行。此外，将在测试用例执行步骤中执行或被执行的测试用例的测试结果添加到源代码中。

4. 发明授权

US09740592B2 Supporting debugging of program and graphical user interface for supporting debugging 有权
公开(公告)号：US09740592B2
公开(公告)日：2017-08-22
申请号：US13593523
申请日：2012-08-24
申请人： Takehiko Amano , Susumu Fukuda , Kenya Ishimoto , Ken Kumagai , Mayumi Takahashi , Atsushi Yokoi
发明人： Takehiko Amano , Susumu Fukuda , Kenya Ishimoto , Ken Kumagai , Mayumi Takahashi , Atsushi Yokoi
IPC分类号： G06F11/36 , G06F9/44
CPC分类号： G06F11/3636 , G06F8/77 , G06F11/3624 , G06F11/3664 , G06F11/3676
摘要： The present invention provides for debugging a target program with a computer comprising a storage unit and a processing unit. In one aspect, this comprises: storing, in the storage unit, reliability information including the reliability of individual indices of classification items of the program; reading, by the processing unit, the reliability information of the target program from the storage unit and determining a reliable code area and an unreliable code area by using the reliability of the individual indices in the reliability information; and executing debugging of the debug target program only for the unreliable code area while omitting debugging of the reliable code area. A graphical user interface to support debugging of only unreliable code areas is also disclosed.

5. 发明授权

US07660148B2 Nonvolatile memory device and method to control the same 有权
标题翻译：非易失存储器件及其控制方法相同
公开(公告)号：US07660148B2
公开(公告)日：2010-02-09
申请号：US12060710
申请日：2008-04-01
申请人： Atsushi Yokoi
发明人： Atsushi Yokoi
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/75 , G11C2213/76 , G11C2213/79
摘要： A nonvolatile memory device is disclosed. The nonvolatile memory device includes a source selector transistor connected at one end thereof to a source line, a plurality of cell selector transistors connected in series with each other and to the other end of said source selector transistor and a basic memory unit including a variable resistor element which is constituted as a memory element to store bit information and is provided for each of said cell selector transistors, being connected at one end thereof to the drain terminal of said cell selector transistor and connected at the other end thereof to the bit line. The source selector transistor and said cell selector transistor provided between one end of said variable resistor element to be accessed and said source line are controlled to turn on.
摘要翻译：公开了非易失性存储器件。非易失性存储器件包括：源极选择晶体管，其一端连接到源极线，多个单元选择晶体管彼此串联连接，并连接到所述源选择晶体管的另一端;以及基本存储单元，包括可变电阻器元件，其构成为用于存储位信息的存储元件，并且为每个所述单元选择晶体管提供，其一端连接到所述单元选择晶体管的漏极端子，并在其另一端连接到位线。设置在要访问的可变电阻元件的一端和所述源极线之间的源选择器晶体管和所述单元选择晶体管被控制为导通。

6. 发明申请

US20060114722A1 Nonvolatile memory device, and its manufacturing method 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US20060114722A1
公开(公告)日：2006-06-01
申请号：US11291048
申请日：2005-11-29
申请人： Atsushi Yokoi , Masao Nakano
发明人： Atsushi Yokoi , Masao Nakano
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C11/5621 , G11C2211/5611 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/7887 , H01L29/7923
摘要： On a channel region enclosed by a pair of diffusion layers 13A, 13B, a first insulating layer 15, a charge accumulative layer 17, and a second insulating layer 19 are stacked up in this order, and on the second insulating layer 19, two control gate layers 21A, 21B spaced across a gap G1 are disposed in the middle of the channel width direction. The charge accumulative layer 17 has discrete charge traps, and, accordingly, movement of charge in the layer is limited. In the charge accumulative layer 17, the charges injected depend on the writing voltage applied in control gate layers 21A, 21B and can be localized beneath the control gate layers 21A, 21B through which a writing voltage is applied. The presence or absence of charges can be controlled in every charge accumulative region beneath the control gate layers 21A, 21B, so that multi-value storage in the memory cell can be realized.
摘要翻译：在由一对扩散层13A，13B，第一绝缘层15，电荷累积层17和第二绝缘层19围绕的沟道区域上依次层叠，在第二绝缘层19上，在间隙G 1间隔开的两个控制栅极层21A，21B设置在沟道宽度方向的中间。电荷累积层17具有离散的电荷陷阱，因此层中的电荷的移动受到限制。在电荷累积层17中，注入的电荷取决于施加在控制栅极层21A，21B中的写入电压，并且可以位于施加写入电压的控制栅极层21A，21B的下方。可以在控制栅极层21A，21B下方的每个电荷累积区域中控制电荷的存在或不存在，从而可以实现存储单元中的多值存储。

7. 发明授权

US5566080A Method and apparatus for designing semiconductor device 失效
标题翻译：用于设计半导体器件的方法和设备
公开(公告)号：US5566080A
公开(公告)日：1996-10-15
申请号：US297101
申请日：1994-08-29
申请人： Atsushi Yokoi
发明人： Atsushi Yokoi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed is a method of designing a semiconductor device including a plurality of elements, using a computer-aided design (CAD) apparatus. Data about the basic design of each cell is stored as a cell in a library of the CAD apparatus. In each cell, a plurality of connecting terminal regions for connecting an associated element to an external interconnection are provided as electrically disconnected from an internal circuit forming area of this element. This cell is laid at a desired position in a semiconductor device that is being designed. After the necessary cells are laid out, one of the connecting terminals is selected for each cell from a plurality of connecting terminal regions. Then, an interconnection for connecting the internal circuit forming area to the selected connecting terminal region is designed.
摘要翻译：公开了使用计算机辅助设计（CAD）设备来设计包括多个元件的半导体器件的方法。关于每个单元的基本设计的数据作为单元存储在CAD设备的库中。在每个单元中，用于将相关元件连接到外部互连件的多个连接端子区域被设置为与该元件的内部电路形成区域电气断开。将该电池放置在正在设计的半导体器件中的期望位置。在布置必要的单元之后，从多个连接端子区域为每个单元选择一个连接端子。然后，设计用于将内部电路形成区域连接到所选择的连接端子区域的互连。

8. 发明授权

US08875104B2 Efficiently developing software using test cases to check the conformity of the software to the requirements 有权
标题翻译：使用测试用例高效开发软件，以检查软件是否符合要求
公开(公告)号：US08875104B2
公开(公告)日：2014-10-28
申请号：US13273478
申请日：2011-10-14
申请人： Atsushi Yokoi
发明人： Atsushi Yokoi
IPC分类号： G06F9/45 , G06F11/00 , G06F11/36
CPC分类号： G06F11/3684 , G06F11/3624
摘要： A method, system and computer program product for efficiently developing software and supporting creation of source code so as to develop software that meets the requirements. A plurality of test cases defining a plurality of respective tests to be executed to check the conformity of the software to the requirements are used. In a test execution step, one or more specific test cases selected from the plurality of test cases are executed or the specific test cases are caused to be executed. Furthermore, a test result of a test case executed or caused to be executed in the test case execution step is added to the source code.
摘要翻译：一种方法，系统和计算机程序产品，用于高效开发软件并支持创建源代码，以开发满足要求的软件。使用定义要执行的多个相应测试的多个测试用例来检查软件与要求的一致性。在测试执行步骤中，执行从多个测试用例中选择的一个或多个特定测试用例，或者使特定测试用例被执行。此外，将在测试用例执行步骤中执行或被执行的测试用例的测试结果添加到源代码中。

9. 发明申请

US20120167055A1 EFFICIENTLY DEVELOPING SOFTWARE USING TEST CASES TO CHECK THE CONFORMITY OF THE SOFTWARE TO THE REQUIREMENTS 有权
标题翻译：使用测试案例检查软件符合要求的有效开发软件
公开(公告)号：US20120167055A1
公开(公告)日：2012-06-28
申请号：US13410000
申请日：2012-03-01
申请人： Atsushi Yokoi
发明人： Atsushi Yokoi
IPC分类号： G06F11/36
CPC分类号： G06F11/3684 , G06F11/3624
摘要： A method for efficiently developing software and supporting creation of source code so as to develop software that meets the requirements. A plurality of test cases defining a plurality of respective tests to be executed to check the conformity of the software to the requirements are used. In a test execution step, one or more specific test cases selected from the plurality of test cases are executed or the specific test cases are caused to be executed. Furthermore, a test result of a test case executed or caused to be executed in the test case execution step is added to the source code.
摘要翻译：一种有效开发软件并支持创建源代码以开发满足要求的软件的方法。使用定义要执行的多个相应测试的多个测试用例来检查软件与要求的一致性。在测试执行步骤中，执行从多个测试用例中选择的一个或多个特定测试用例，或者使特定测试用例被执行。此外，将在测试用例执行步骤中执行或被执行的测试用例的测试结果添加到源代码中。

10. 发明申请

US20080266934A1 NONVOLATILE MEMORY DEVICE AND METHOD TO CONTROL THE SAME 有权
标题翻译：非易失性存储器件及其控制方法
公开(公告)号：US20080266934A1
公开(公告)日：2008-10-30
申请号：US12060710
申请日：2008-04-01
申请人： Atsushi Yokoi
发明人： Atsushi Yokoi
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/75 , G11C2213/76 , G11C2213/79
摘要： A nonvolatile memory device is disclosed. The nonvolatile memory device includes a source selector transistor connected at one end thereof to a source line, a plurality of cell selector transistors connected in series with each other and to the other end of said source selector transistor and a basic memory unit including a variable resistor element which is constituted as a memory element to store bit information and is provided for each of said cell selector transistors, being connected at one end thereof to the drain terminal of said cell selector transistor and connected at the other end thereof to the bit line. The source selector transistor and said cell selector transistor provided between one end of said variable resistor element to be accessed and said source line are controlled to turn on.
摘要翻译：公开了非易失性存储器件。非易失性存储器件包括：源极选择晶体管，其一端连接到源极线，多个单元选择晶体管彼此串联连接，并连接到所述源选择晶体管的另一端;以及基本存储单元，包括可变电阻器元件，其构成为用于存储位信息的存储元件，并且为每个所述单元选择晶体管提供，其一端连接到所述单元选择晶体管的漏极端子，并在其另一端连接到位线。设置在要访问的可变电阻元件的一端和所述源极线之间的源选择器晶体管和所述单元选择晶体管被控制为导通。

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