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    • 3. 发明授权
    • Low-power analog-circuit architecture for decoding neural signals
    • 用于解码神经信号的低功耗模拟电路架构
    • US08352385B2
    • 2013-01-08
    • US12127380
    • 2008-05-27
    • Benjamin I. RapoportRahul SarpeshkarWoradorn Wattanapanitch
    • Benjamin I. RapoportRahul SarpeshkarWoradorn Wattanapanitch
    • G06F15/18
    • A61B5/04001G06F3/015G06K9/00536
    • A microchip for performing a neural decoding algorithm is provided. The microchip is implemented using ultra-low power electronics. Also, the microchip includes a tunable neural decodable filter implemented using a plurality of amplifiers, a plurality of parameter learning filters, a multiplier, a gain and time-constant biasing circuits; and analog memory. The microchip, in a training mode, learns to perform an optimized translation of a raw neural signal received from a population of cortical neurons into motor control parameters. The optimization being based on a modified gradient descent least square algorithm wherein update for a given parameter in a filter is proportional to an averaged product of an error in the final output that the filter affects and a filtered version of its input. The microchip, in an operational mode, issues commands to controlling a device using learned mappings.
    • 提供了一种用于执行神经解码算法的微芯片。 微芯片采用超低功耗电子器件实现。 此外,微芯片包括使用多个放大器实现的可调谐神经可解码滤波器,多个参数学习滤波器,乘法器,增益和时间常数偏置电路; 和模拟记忆。 在训练模式下,微芯片学习了将从皮质神经元群体接收的原始神经信号转化为电动机控制参数的优化翻译。 该优化基于修正的梯度下降最小二乘算法,其中过滤器中的给定参数的更新与滤波器影响的最终输出中的误差和其输入的滤波版本的平均乘积成比例。 在操作模式下,微芯片发出使用学习映射控制设备的命令。
    • 4. 发明申请
    • LOW-POWER ANALOG-CIRCUIT ARCHITECTURE FOR DECODING NEURAL SIGNALS
    • 用于解码神经信号的低功耗模拟电路架构
    • US20080294579A1
    • 2008-11-27
    • US12127380
    • 2008-05-27
    • Benjamin I. RapoportRahul SarpeshkarWoradorn Wattanapanitch
    • Benjamin I. RapoportRahul SarpeshkarWoradorn Wattanapanitch
    • G06F15/18
    • A61B5/04001G06F3/015G06K9/00536
    • A microchip for performing a neural decoding algorithm is provided. The microchip is implemented using ultra-low power electronics. Also, the microchip includes a tunable neural decodable filter implemented using a plurality of amplifiers, a plurality of parameter learning filters, a multiplier, a gain and time-constant biasing circuits; and analog memory. The microchip, in a training mode, learns to perform an optimized translation of a raw neural signal received from a population of cortical neurons into motor control parameters. The optimization being based on a modified gradient descent least square algorithm wherein update for a given parameter in a filter is proportional to an averaged product of an error in the final output that the filter affects and a filtered version of its input. The microchip, in an operational mode, issues commands to controlling a device using learned mappings.
    • 提供了一种用于执行神经解码算法的微芯片。 微芯片采用超低功耗电子器件实现。 此外,微芯片包括使用多个放大器实现的可调谐神经可解码滤波器,多个参数学习滤波器,乘法器,增益和时间常数偏置电路; 和模拟记忆。 在训练模式下,微芯片学习了将从皮质神经元群体接收的原始神经信号转化为电动机控制参数的优化翻译。 该优化基于修正的梯度下降最小二乘算法,其中过滤器中给定参数的更新与滤波器影响的最终输出中的误差和其输入的滤波版本的平均乘积成比例。 在操作模式下,微芯片发出使用学习映射控制设备的命令。