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1. 发明申请

US20150349142A1 SPLIT GATE MEMORY CELL WITH IMPROVED ERASE PERFORMANCE 有权
标题翻译：具有改进的擦除性能的分离器门存储器单元
公开(公告)号：US20150349142A1
公开(公告)日：2015-12-03
申请号：US14288975
申请日：2014-05-28
申请人： BRIAN A. WINSTEAD , Ko-Min Chang , Craig T. Swift
发明人： BRIAN A. WINSTEAD , Ko-Min Chang , Craig T. Swift
IPC分类号： H01L29/792 , H01L29/51 , H01L21/28 , G11C16/14
CPC分类号： H01L21/28282 , G11C16/0425 , H01L21/28273 , H01L29/42328 , H01L29/42332 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer.
摘要翻译：半导体器件包括半导体衬底，在衬底的一部分上的电荷存储堆叠。电荷存储堆叠包括第一电介质层，与第一介电层接触的纳米晶体层，与纳米晶体层接触并与其接触的第二电介质层，在第二介电层上并与第二介电层接触的氮化物层，以及在氮化物层上的第三电介质层。

2. 发明授权

US09425055B2 Split gate memory cell with a layer of nanocrystals with improved erase performance 有权
标题翻译：分离栅极存储单元与一层纳米晶体，具有改进的擦除性能
公开(公告)号：US09425055B2
公开(公告)日：2016-08-23
申请号：US14288975
申请日：2014-05-28
申请人： Brian A. Winstead , Ko-Min Chang , Craig T. Swift
发明人： Brian A. Winstead , Ko-Min Chang , Craig T. Swift
IPC分类号： G11C16/04 , H01L21/28 , H01L29/78 , H01L29/423 , H01L29/788
CPC分类号： H01L21/28282 , G11C16/0425 , H01L21/28273 , H01L29/42328 , H01L29/42332 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer.
摘要翻译：半导体器件包括半导体衬底，在衬底的一部分上的电荷存储堆叠。电荷存储堆叠包括第一电介质层，与第一介电层接触的纳米晶体层，与纳米晶体层接触并与其接触的第二电介质层，在第二介电层上并与第二介电层接触的氮化物层，以及在氮化物层上的第三电介质层。

3. 发明授权

US07582929B2 Electronic device including discontinuous storage elements 有权
标题翻译：电子设备包括不连续的存储元件
公开(公告)号：US07582929B2
公开(公告)日：2009-09-01
申请号：US11188999
申请日：2005-07-25
申请人： Michael A. Sadd , Ko-Min Chang , Gowrishankar L. Chindalore , Cheong M. Hong , Craig T. Swift
发明人： Michael A. Sadd , Ko-Min Chang , Gowrishankar L. Chindalore , Cheong M. Hong , Craig T. Swift
IPC分类号： H01L29/94
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825
摘要： An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein at least one discontinuous storage element lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and a primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
摘要翻译：电子设备可以包括位于沟槽内的不连续存储元件。在一个实施例中，电子设备可以包括具有包括壁和底部的沟槽的衬底。电子设备还可以包括位于沟槽内的不连续存储元件的一部分。电子器件还可以包括第一栅电极，其中至少一个不连续存储元件沿着沟槽的壁位于第一栅电极的上表面和衬底的主表面之间的高度处。电子器件还可以包括覆盖在第一栅电极和衬底的主表面上的第二栅电极。在另一个实施例中，导线可以电连接到一个或多个存储单元的行或列，而另一个导线可以是更多行或更多列的存储单元。

4. 发明授权

US06791883B2 Program and erase in a thin film storage non-volatile memory 有权
标题翻译：在薄膜存储非易失性存储器中编程和擦除
公开(公告)号：US06791883B2
公开(公告)日：2004-09-14
申请号：US10178658
申请日：2002-06-24
申请人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
发明人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
IPC分类号： G11C1600
CPC分类号： G11C16/0466
摘要： A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.
摘要翻译：具有薄膜电介质存储元件的非易失性存储器通过热载流子注入（HCI）编程并通过隧道擦除。这种存储器的存储单元的典型结构是硅，氧化物，氮化物，氧化物和硅（SONOS）。热载波注入为SONOS提供相对快速的编程，而隧道提供擦除，避免了通常伴随热载流子注入进行编程的热孔擦除（HHE）类型擦除的困难。 HHE对电介质的破坏性更大，导致可靠性问题。 HHE还具有相对较窄的擦除区域，可能不完全匹配HCI编程的模式，从而导致不完整的擦除。隧道擦除有效地覆盖整个区域，所以不用担心不完全擦除。虽然隧道擦除比HHE慢，但擦除时间在系统操作中通常不如编程时间那么重要。

5. 发明授权

US07619275B2 Process for forming an electronic device including discontinuous storage elements 失效
标题翻译：用于形成包括不连续存储元件的电子设备的方法
公开(公告)号：US07619275B2
公开(公告)日：2009-11-17
申请号：US11188935
申请日：2005-07-25
申请人： Michael A. Sadd , Ko-Min Chang , Gowrishankar L. Chindalore , Cheong M. Hong , Craig T. Swift
发明人： Michael A. Sadd , Ko-Min Chang , Gowrishankar L. Chindalore , Cheong M. Hong , Craig T. Swift
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0475 , H01L21/7624 , H01L27/11519 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336
摘要： A process for forming an electronic device can include forming a trench within a substrate, wherein the trench includes a wall and a bottom. The process can also include including forming a portion of discontinuous storage elements that lie within the trench, and forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also include forming a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
摘要翻译：用于形成电子器件的方法可以包括在衬底内形成沟槽，其中沟槽包括壁和底部。该方法还可以包括形成位于沟槽内的不连续存储元件的一部分，以及在形成不连续存储元件之后在沟槽内形成第一栅电极。至少一个不连续的存储元件位于第一栅电极的上表面和衬底的主表面之间的海拔处的沟槽的壁处。该工艺还可以包括形成覆盖在第一栅电极和衬底的主表面上的第二栅电极。

6. 发明授权

US09136360B1 Methods and structures for charge storage isolation in split-gate memory arrays 有权
标题翻译：分闸存储器阵列中电荷存储隔离的方法和结构
公开(公告)号：US09136360B1
公开(公告)日：2015-09-15
申请号：US14297657
申请日：2014-06-06
申请人： Asanga H. Perera , Ko-Min Chang , Craig T. Swift
发明人： Asanga H. Perera , Ko-Min Chang , Craig T. Swift
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L29/66833 , H01L27/11521 , H01L29/42328 , H01L29/66825
摘要： Forming a memory structure includes forming a charge storage layer over a substrate; forming a first control gate layer; patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate; filling the opening with an insulating material; forming a second control gate layer over the patterned first control gate layer and the insulating material; patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and the insulating material is between the control gate electrodes; and forming select gate electrodes adjacent the control gate electrodes.
摘要翻译：形成存储器结构包括在衬底上形成电荷存储层; 形成第一控制栅层; 图案化第一控制栅极层以在第一控制栅极层和电荷存储层中形成开口，其中开口延伸到基板中; 用绝缘材料填充开口; 在所述图案化的第一控制栅极层和绝缘材料上形成第二控制栅极层; 图案化第二控制栅极层以形成第一控制栅电极和第二控制栅电极，其中第一控制栅电极包括第一和第二控制栅层中的每一个的第一部分，而第二控制栅电极包括第二部分并且所述绝缘材料位于所述控制栅电极之间; 以及在控制栅电极附近形成选择栅电极。

7. 发明授权

US09105748B1 Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor 有权
标题翻译：集成非易失性存储器（NVM）单元和逻辑晶体管及其方法
公开(公告)号：US09105748B1
公开(公告)日：2015-08-11
申请号：US14480017
申请日：2014-09-08
申请人： Asanga H. Perera , Craig T. Swift
发明人： Asanga H. Perera , Craig T. Swift
IPC分类号： H01L27/115 , H01L21/8239
CPC分类号： H01L21/8239 , H01L27/11521 , H01L27/11524 , H01L27/11536 , H01L27/11539 , H01L27/11543 , H01L29/66545
摘要： A method of making a split gate non-volatile memory (NVM) using a substrate includes etching a recess into an isolation region of an NVM region of the substrate and depositing a conductive layer and a capping layer. A select gate and a control gate are formed in the NVM region, and a dummy gate is formed in a logic region of the substrate. A portion of the capping layer is removed and a salicide block bi-layer is deposited and patterned to form a first opening that exposes a contact portion of the conductive layer over the recess. A silicided region is formed on the contact portion. The substrate is planarized to expose the dummy gate, which is replaced with a metal gate. A second opening is etched through a first interlayer dielectric deposited over the substrate to the silicided region. Contact metal is deposited into the second opening.
摘要翻译：使用衬底制造分离栅极非易失性存储器（NVM）的方法包括将凹陷蚀刻到衬底的NVM区域的隔离区域中并沉积导电层和覆盖层。在NVM区域中形成选择栅极和控制栅极，并且在衬底的逻辑区域中形成伪栅极。去除覆盖层的一部分，并且沉积硅化物嵌段双层并图案化以形成将导电层的接触部分暴露在凹部上的第一开口。在接触部分上形成硅化区域。将衬底平坦化以暴露伪栅极，其被金属栅极替代。通过沉积在衬底上的第一层间电介质蚀刻第二个开口到硅化物区域。接触金属沉积到第二个开口中。

8. 发明授权

US07679125B2 Back-gated semiconductor device with a storage layer and methods for forming thereof 有权
标题翻译：具有存储层的后门控半导体器件及其形成方法
公开(公告)号：US07679125B2
公开(公告)日：2010-03-16
申请号：US11300077
申请日：2005-12-14
申请人： Craig T. Swift , Gowrishankar L. Chindalore , Thuy B. Dao , Michael A. Sadd
发明人： Craig T. Swift , Gowrishankar L. Chindalore , Thuy B. Dao , Michael A. Sadd
IPC分类号： H01L29/76
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L21/84 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.
摘要翻译：制造半导体器件的方法包括提供第一晶片并提供具有第一侧和第二侧的第二晶片，所述第二晶片包括半导体衬底，存储层和栅极材料层。存储层可以位于半导体结构和栅极材料层之间，并且存储层可以比半导体结构更靠近第二晶片的第一侧。该方法还包括将第二晶片的第一侧布置到第一晶片。该方法还包括去除半导体结构的第一部分以在结合之后留下半导体结构层。该方法还包括形成具有沟道区的晶体管，其中沟道区的至少一部分由半导体结构的层形成。

9. 发明授权

US07205608B2 Electronic device including discontinuous storage elements 有权
标题翻译：电子设备包括不连续的存储元件
公开(公告)号：US07205608B2
公开(公告)日：2007-04-17
申请号：US11188910
申请日：2005-07-25
申请人： Gowrishankar L. Chindalore , Cheong M. Hong , Craig T. Swift
发明人： Gowrishankar L. Chindalore , Cheong M. Hong , Craig T. Swift
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7887 , B82Y10/00 , G11C16/0475 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825 , Y10S977/707 , Y10S977/712
摘要： An electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a first set of discontinuous storage elements that overlie a primary surface of the substrate and a second set of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein substantially none of the discontinuous storage elements lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and the primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
摘要翻译：电子设备可以包括具有包括壁和底部的沟槽的衬底。电子设备还可以包括覆盖在衬底的主表面上的第一组不连续存储元件和位于沟槽内的第二组不连续存储元件。电子器件还可以包括第一栅电极，其中在第一栅电极和衬底的主表面之间的上表面和第一栅极电极的上表面之间基本上不存在不连续的存储元件沿着沟槽的壁。电子器件还可以包括覆盖第一栅电极和主表面的第二栅电极。在另一个实施例中，导线可以电连接到一个或多个存储单元的行或列，而另一个导线可以是更多行或更多列的存储单元。

10. 发明授权

US07094645B2 Programming and erasing structure for a floating gate memory cell and method of making 有权
标题翻译：浮动存储单元的编程和擦除结构及其制作方法
公开(公告)号：US07094645B2
公开(公告)日：2006-08-22
申请号：US10944239
申请日：2004-09-17
申请人： Craig T. Swift , Gowrishankar L. Chindalore
发明人： Craig T. Swift , Gowrishankar L. Chindalore
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A floating gate memory cell has a floating gate in which there are two adjacent floating gate layers. The top layer is made to have a contour while leaving the lower layer substantially unchanged. An interlevel dielectric and a control gate follow the contour of the floating gate to increase capacitance between the control gate and the floating gate. The two layers of the floating gate can be polysilicon in which the top layer has the contour formed therein by use of a sacrificial layer. The sacrificial layer is formed over the bottom polysilicon layer and etched. The top polysilicon layer is formed over the sacrificial layer. Subsequent processing of the top polysilicon layer exposes the remaining portion of the sacrificial layer so it can be removed; leaving the contour in the top polysilicon layer for the interlevel dielectric and the control gate.
摘要翻译：浮动栅极存储单元具有浮置栅极，其中存在两个相邻的浮置栅极层。顶层制成具有轮廓，同时使下层基本上保持不变。一个层间电介质和一个控制栅极跟随着浮栅的轮廓，以增加控制栅和浮栅之间的电容。浮栅的两层可以是多晶硅，其中顶层具有通过使用牺牲层形成在其中的轮廓。牺牲层形成在底部多晶硅层上并被蚀刻。顶部多晶硅层形成在牺牲层上。顶部多晶硅层的后续处理暴露了牺牲层的剩余部分，使得其可以被去除; 将轮廓留在层间电介质和控制栅极的顶部多晶硅层中。

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