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1. 发明授权

US08766349B2 Semiconductor device having stacked array structure, NAND flash memory array using the same and fabrication thereof 有权
标题翻译：具有堆叠阵列结构的半导体器件，使用其的NAND闪存阵列及其制造
公开(公告)号：US08766349B2
公开(公告)日：2014-07-01
申请号：US13383097
申请日：2009-12-22
申请人： Byung Gook Park , Jang Gn Yun , Il Han Park
发明人： Byung Gook Park , Jang Gn Yun , Il Han Park
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11565 , H01L27/11578 , H01L27/11582
摘要： The present invention relates to a semiconductor device, a memory array and a fabrication method thereof, and more particularly to a semiconductor device having a stacked array structure (referred to as a STAR structure: a STacked ARray structure) applicable to not only a switch device but also a memory device, a NAND flash memory array using the same as a memory device and a fabrication method thereof.
摘要翻译：本发明涉及一种半导体器件，存储器阵列及其制造方法，更具体地说，涉及一种具有堆叠阵列结构（简称为STAR结构：堆叠式ARray结构）的半导体器件，其不仅适用于开关器件而且还包括使用与存储器件相同的存储器件，NAND闪存阵列及其制造方法。

2. 发明授权

US07863643B2 Memory cell device having vertical channel and double gate structure 有权
标题翻译：具有垂直沟道和双栅结构的存储单元器件
公开(公告)号：US07863643B2
公开(公告)日：2011-01-04
申请号：US12309959
申请日：2007-09-20
申请人： Byung Gook Park , Il Han Park
发明人： Byung Gook Park , Il Han Park
IPC分类号： H01L29/66
CPC分类号： H01L27/115 , H01L27/11568
摘要： A memory cell device having a vertical channel and a double gate structure is provided. More specifically, a memory cell device having a vertical channel and a double gate structure is characterized by having a pillar active region with a predetermined height, which is including a first semiconductor layer forming a first source/drain region, a second semiconductor layer being placed under the first semiconductor layer with a predetermined distance and forming a second source/drain region, and a third semiconductor layer forming a body region and a channel region between the first semiconductor layer and the second semiconductor layer, and therefore, there is no need for unnecessary contacts when it is used as a unit cell for any type of memory array, not to speak of NOR type flash memory array. And the present invention makes to program/erase more effectively and increase the read speed and the amount of sensing current.
摘要翻译：提供具有垂直通道和双栅极结构的存储单元器件。更具体地说，具有垂直沟道和双栅极结构的存储单元器件的特征在于具有预定高度的柱状有源区，其包括形成第一源极/漏极区的第一半导体层，放置第二半导体层的第二半导体层在第一半导体层之下具有预定距离并形成第二源极/漏极区域，以及形成第一半导体层和第二半导体层之间的体区域和沟道区域的第三半导体层，因此不需要当它被用作任何类型的存储器阵列的单位单元时，不用说NOR型闪存阵列就是不必要的接触。并且本发明使得更有效地编程/擦除并增加读取速度和感测电流的量。

3. 发明申请

US20120117316A1 SEMICONDUCTOR DEVICE HAVING STACKED ARRAY STRUCTURE, NAND FLASH MEMORY ARRAY USING THE SAME AND FABRICATION THEREOF 有权
标题翻译：具有堆叠阵列结构的半导体器件，使用其的NAND闪存存储器阵列及其制造方法
公开(公告)号：US20120117316A1
公开(公告)日：2012-05-10
申请号：US13383097
申请日：2009-12-22
申请人： Byung Gook Park , Jang Gn Yun , Il Han Park
发明人： Byung Gook Park , Jang Gn Yun , Il Han Park
IPC分类号： G06F12/02
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11565 , H01L27/11578 , H01L27/11582
摘要： The present invention relates to a semiconductor device, a memory array and a fabrication method thereof, and more particularly to a semiconductor device having a stacked array structure (referred to as a STAR structure: a STacked ARray structure) applicable to not only a switch device but also a memory device, a NAND flash memory array using the same as a memory device and a fabrication method thereof.
摘要翻译：本发明涉及一种半导体器件，存储器阵列及其制造方法，更具体地说，涉及一种具有堆叠阵列结构（简称为STAR结构：堆叠式ARray结构）的半导体器件，其不仅适用于开关器件而且还包括使用其作为存储器件的存储器件，NAND闪速存储器阵列及其制造方法。

4. 发明授权

US08324060B2 NAND flash memory array having pillar structure and fabricating method of the same 有权
标题翻译：具有柱结构的NAND闪存阵列及其制造方法
公开(公告)号：US08324060B2
公开(公告)日：2012-12-04
申请号：US13222246
申请日：2011-08-31
申请人： Byung Gook Park , Seong Jae Cho
发明人： Byung Gook Park , Seong Jae Cho
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A method is provided for fabricating a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. The NAND flash memory array has insulator strip structure and one or more semiconductor strips are next to the both sides of the insulator strip. The NAND flash memory array allows for an improvement of the integrity by decreasing the memory cell area by half and less, and solves the problems of the conventional three-dimensional structure regarding isolation between not only channels but also source/drain regions at the bottom of trenches. The method for fabricating the NAND flash memory array having a pillar structure uses the conventional CMOS process and an etching process with minimum masks, enables to cut down costs.
摘要翻译：提供了一种用于制造具有垂直沟道和侧壁栅极结构的NAND快闪存储器阵列的方法及其制造方法。 NAND闪存阵列具有绝缘体带结构，并且一个或多个半导体条紧邻绝缘体条的两侧。 NAND闪存阵列允许通过将存储器单元面积减小一半或更少来提高整体性，并且解决了传统的三维结构关于不仅仅是通道之间的隔离的问题，而且解决了底部的源极/漏极区域沟渠制造具有柱状结构的NAND快闪存储器阵列的方法使用传统的CMOS工艺和具有最小掩模的蚀刻工艺，能够降低成本。

5. 发明授权

US06335245B1 Method for fabricating single electron transistor 有权
公开(公告)号：US06335245B1
公开(公告)日：2002-01-01
申请号：US09794357
申请日：2001-02-28
申请人： Byung Gook Park , Dae Hwan Kim
发明人： Byung Gook Park , Dae Hwan Kim
IPC分类号： H01L21336
摘要： A fabrication method provides a single electron transistor with a reduced quantum dot size. The method includes the steps of forming a first gate insulating film on a semiconductor substrate, implanting impurity ions into source/drain regions of the semiconductor substrate to form source/drain impurity regions, forming a lower gate on the first gate insulating film over a channel region between the source/drain impurity regions, forming a second gate insulating film on the lower gate and the first gate insulating film, forming a third insulating film on the second gate insulating film, selectively removing a portion of the third insulating film over the channel region in a direction perpendicular to a direction between the source/drain impurity regions to define a groove in the third insulating film, and forming an upper gate in he groove of the third insulating film.

6. 发明申请

US20120058619A1 NAND FLASH MEMORY ARRAY HAVING PILLAR STRUCTURE AND FABRICATING METHOD OF THE SAME 有权
标题翻译：具有支柱结构的NAND闪存阵列及其制造方法
公开(公告)号：US20120058619A1
公开(公告)日：2012-03-08
申请号：US13222246
申请日：2011-08-31
申请人： Byung Gook Park , Seong Jae Cho
发明人： Byung Gook Park , Seong Jae Cho
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A method is provided for fabricating a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. The NAND flash memory array has insulator strip structure and one or more semiconductor strips are next to the both sides of the insulator strip. The NAND flash memory array allows for an improvement of the integrity by decreasing the memory cell area by half and less, and solves the problems of the conventional three-dimensional structure regarding isolation between not only channels but also source/drain regions at the bottom of trenches. The method for fabricating the NAND flash memory array having a pillar structure uses the conventional CMOS process and an etching process with minimum masks, enables to cut down costs.
摘要翻译：提供了一种用于制造具有垂直沟道和侧壁栅极结构的NAND快闪存储器阵列的方法及其制造方法。 NAND闪存阵列具有绝缘体带结构，并且一个或多个半导体条紧邻绝缘体条的两侧。 NAND闪存阵列允许通过将存储器单元面积减小一半或更少来提高整体性，并且解决了传统的三维结构关于不仅仅是通道之间的隔离的问题，而且解决了底部的源极/漏极区域沟渠制造具有柱状结构的NAND快闪存储器阵列的方法使用传统的CMOS工艺和具有最小掩模的蚀刻工艺，能够降低成本。

7. 发明申请

US20110273410A1 LED DISPLAY APPARATUS HAVING ACTIVE DEVICES AND FABRICATION METHOD THEREOF 有权
标题翻译：具有活动装置的LED显示装置及其制造方法
公开(公告)号：US20110273410A1
公开(公告)日：2011-11-10
申请号：US13095295
申请日：2011-04-27
申请人： Byung Gook Park , Chang Su Seo , Byung Doo Yoo , Keun Kee Hong , Sang Yeop Jee , Jae Min Jeong
发明人： Byung Gook Park , Chang Su Seo , Byung Doo Yoo , Keun Kee Hong , Sang Yeop Jee , Jae Min Jeong
IPC分类号： G09G3/32 , H01L33/62 , G06F3/038
CPC分类号： H01L25/167 , H01L24/95 , H01L27/1214 , H01L27/1255 , H01L33/20 , H01L33/40 , H01L2224/95085 , H01L2924/01322 , H01L2924/12036 , H01L2924/12041 , H01L2924/12044 , H01L2924/00
摘要： An active matrix LED display apparatus and a fabrication method thereof are provided. The active matrix LED display apparatus enables to miniaturize pixel by a formation of wiring on bottom layer and an assembly of each block through each eutectic layer into each transistor block receptor and/or each LED block receptor formed according to each color element unit, and to be embodied with high luminance, low power consumption, high reliability and superior optical property by assembling a transistor block having high electron mobility. And the fabricating method of the present invention enables to make efficiently an AM-LED display apparatus at room temperature in a short time by using different shapes of receptor and block depending on the function of a transistor and/or on the color of an LED.
摘要翻译：提供一种有源矩阵LED显示装置及其制造方法。有源矩阵LED显示装置能够通过在底层上形成布线并且通过每个共晶层将每个块的组合分成每个根据每个色素单元形成的每个晶体管块接收器和/或每个LED块接收器来使像素小型化，并且通过组装具有高电子迁移率的晶体管块，具有高亮度，低功耗，高可靠性和优异的光学性能。本发明的制造方法能够根据晶体管的功能和/或LED的颜色，通过使用不同形状的接收器和块来在短时间内在室温下有效地制造AM-LED显示装置。

8. 发明申请

US20100015773A1 SONOS MEMORY DEVICE HAVING CURVED SURFACE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有弯曲表面的SONOS存储器件及其制造方法
公开(公告)号：US20100015773A1
公开(公告)日：2010-01-21
申请号：US12482355
申请日：2009-06-10
申请人： Byung Gook Park , Jung Hoon Lee
发明人： Byung Gook Park , Jung Hoon Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/1033 , H01L29/4232 , H01L29/66833 , H01L29/7854
摘要： A new SONOS memory device is provided, in which a conventional planar surface of multi-dielectric layers (ONO layers) is instead formed with a curved surface such as a cylindrical shape, and included is a method for fabricating the same.A radius of curvature of the upper surface of a blocking oxide can be designed to be larger than that of the lower surface of a tunneling oxide, which restrains electrons from passing through the blocking oxide by back-tunneling on erasing. As a result, a SONOS memory device shows an improvement in erasing speed.
摘要翻译：提供了一种新的SONOS存储器件，其中多个电介质层（ONO层）的常规平面表面替代地形成有诸如圆柱形的弯曲表面，并且包括其制造方法。阻挡氧化物的上表面的曲率半径可以被设计为大于隧道氧化物的下表面的曲率半径，其阻止电子在擦除时通过反向隧道穿过阻塞氧化物。结果，SONOS存储器件显示出擦除速度的改进。

9. 发明授权

US07915109B2 Semiconductor probe structure using impact-ionization metal oxide semiconductor device, information storing device therewith and manufacturing method thereof 有权
标题翻译：使用冲击电离金属氧化物半导体器件的半导体探针结构，其信息存储装置及其制造方法
公开(公告)号：US07915109B2
公开(公告)日：2011-03-29
申请号：US11957575
申请日：2007-12-17
申请人： Hyoung Soo Ko , Byung Gook Park , Seung Bum Hong , Chul Min Park , Woo Young Choi , Jong Pil Kim , Jae Young Song , Sang Wan Kim
发明人： Hyoung Soo Ko , Byung Gook Park , Seung Bum Hong , Chul Min Park , Woo Young Choi , Jong Pil Kim , Jae Young Song , Sang Wan Kim
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/0847 , H01L29/66636 , H01L29/66659 , H01L29/78
摘要： A method of manufacturing a probe includes: forming a first slant face of the probe through an anisotropic etching process using a first etching mask pattern formed on a silicon substrate; forming a first semiconductor electrode region; forming a second etching mask pattern in an opposite direction of the first etching mask pattern on the silicon substrate; forming a spacer layer on a side wall of the second etching mask pattern; forming a second slant face of the probe; forming a second semiconductor electrode region; forming a silicon oxide layer pattern on the resulting silicon substrate; forming spacer layers on both side walls of the silicon oxide layer pattern; and etching the silicon substrate to a predetermined depth.
摘要翻译：探针的制造方法包括：使用形成在硅衬底上的第一蚀刻掩模图案，通过各向异性蚀刻工艺形成探针的第一倾斜面; 形成第一半导体电极区域; 在所述硅衬底上与所述第一蚀刻掩模图案的相反方向形成第二蚀刻掩模图案; 在所述第二蚀刻掩模图案的侧壁上形成间隔层; 形成探针的第二倾斜面; 形成第二半导体电极区域; 在所得硅衬底上形成氧化硅层图案; 在氧化硅层图案的两个侧壁上形成间隔层; 并将硅衬底蚀刻到预定深度。

10. 发明授权

US07700393B2 Method of manufacturing enhancement type semiconductor probe and information storage device having the semiconductor probe using the same 失效
标题翻译：制造增强型半导体探针的方法和具有使用其的半导体探针的信息存储装置
公开(公告)号：US07700393B2
公开(公告)日：2010-04-20
申请号：US12043982
申请日：2008-03-07
申请人： Hyoung Soo Ko , Byung Gook Park , Seung Bum Hong , Chul Min Park , Woo Young Choi , Jong Pil Kim , Jae Young Song , Sang Wan Kim
发明人： Hyoung Soo Ko , Byung Gook Park , Seung Bum Hong , Chul Min Park , Woo Young Choi , Jong Pil Kim , Jae Young Song , Sang Wan Kim
IPC分类号： H01L21/00
CPC分类号： H01L29/7834 , B82Y10/00 , G11B9/1409 , H01L21/28123 , H01L29/66636
摘要： A method of manufacturing an enhancement type semiconductor probe and an information storage device having the enhancement type semiconductor probe are provided. The method involves using an anisotropic wet etching and a side-wall in which influence of process parameters upon the performance of a device is reduced to improve reliability of the device in mass-production, and factors of degrading measuring sensitivity is removed to improve the performance of the device.
摘要翻译：提供一种制造增强型半导体探针的方法和具有该增强型半导体探针的信息存储装置。该方法包括使用各向异性湿蚀刻和侧壁，其中降低了工艺参数对器件性能的影响，以提高器件在批量生产中的可靠性，并且去除降低测量灵敏度的因素以提高性能的设备。

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