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1. 发明申请

US20220336233A1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 有权
公开(公告)号：US20220336233A1
公开(公告)日：2022-10-20
申请号：US17856039
申请日：2022-07-01
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chih-Ming Kuo , Lung-Hua Ho , You-Ming Hsu , Fei-Jain Wu
IPC分类号： H01L21/56 , H01L23/31 , H01L23/00 , H01L21/78
摘要： A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.

2. 发明授权

US08823169B2 Semiconductor manufacturing method and semiconductor structure thereof 有权
标题翻译：半导体制造方法及其半导体结构
公开(公告)号：US08823169B2
公开(公告)日：2014-09-02
申请号：US13644749
申请日：2012-10-04
申请人： Chipbond Technology Corporation
发明人： Chih-Ming Kuo , Lung-Hua Ho , Shih-Chieh Chang , Chia-Yeh Huang , Chin-Tang Hsieh
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76885 , H01L21/4853 , H01L23/48 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13006 , H01L2224/13016 , H01L2224/13023 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.
摘要翻译：半导体制造方法包括提供载体; 形成第一光致抗蚀剂层; 形成多个芯部; 去除第一光致抗蚀剂层; 形成第二光致抗蚀剂层; 形成多个连接部分，所述多个连接部分中的每一个包括第一连接层和第二连接层，并且连接到每个所述芯部分以形成混合凸块，其中每个所述第一连接层包括基部，突出部分和容纳空间，每个基部包括上表面，每个突出部分突出到上表面并且位于每个芯部的顶部，每个容纳空间位于每个突出部分的外侧，第二连接层覆盖突出部分和上表面，并且容纳空间被第二连接层填充; 去除第二光致抗蚀剂层以露出混合凸块。

3. 发明申请

US20140217578A1 SEMICONDUCTOR PACKAGE PROCESS AND STRUCTURE THEREOF 审中-公开
标题翻译：半导体封装工艺及其结构
公开(公告)号：US20140217578A1
公开(公告)日：2014-08-07
申请号：US13833347
申请日：2013-03-15
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Lung-Hua Ho , Fei-Jain Wu , Chih-Ming Kuo , Shih-Chieh Chang , Chia-Jung Tu
IPC分类号： H01L23/00
CPC分类号： H01L24/81 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/13006 , H01L2224/13016 , H01L2224/13017 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13562 , H01L2224/1601 , H01L2224/16503 , H01L2224/81048 , H01L2224/81193 , H01L2224/81203 , H01L2224/81898 , H01L2924/1461 , H01L2924/00 , H01L2924/00014 , H01L2924/01047 , H01L2924/00012
摘要： A semiconductor package process includes the following steps, providing a first substrate having a first metal bump, the first metal bump comprises a joint portion having a first softening point; providing a second substrate having a second metal bump having a top surface, a lateral surface and a second softening point, wherein the first softening point is smaller than the second softening point; performing a heating procedure to make the joint portion of the first metal bump become a softened state; and laminating the first substrate on the second substrate to make the second metal bump embedded into the joint portion in the softened state to make the top surface and the lateral surface of the at least one second metal bump being clad extendedly by compressing the joint portion in the softened state.
摘要翻译：半导体封装工艺包括以下步骤：提供具有第一金属凸块的第一衬底，第一金属凸块包括具有第一软化点的接合部分; 提供具有第二金属凸块的第二基板，其具有顶表面，侧表面和第二软化点，其中所述第一软化点小于所述第二软化点; 执行加热程序以使第一金属凸块的接合部分变为软化状态; 并且将所述第一基板层压在所述第二基板上，以使所述第二金属凸块以软化状态嵌入所述接合部，以使所述至少一个第二金属凸块的顶表面和所述侧表面通过压缩所述接合部分软化状态。

4. 发明申请

US20140021601A1 SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF 有权
公开(公告)号：US20140021601A1
公开(公告)日：2014-01-23
申请号：US13644749
申请日：2012-10-04
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chih-Ming Kuo , Lung-Hua Ho , Shih-Chieh Chang , Chia-Yeh Huang , Chin-Tang Hsieh
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L21/76885 , H01L21/4853 , H01L23/48 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13006 , H01L2224/13016 , H01L2224/13023 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.

5. 发明申请

US20220037166A1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 有权
公开(公告)号：US20220037166A1
公开(公告)日：2022-02-03
申请号：US17161818
申请日：2021-01-29
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chih-Ming Kuo , Lung-Hua Ho , You-Ming Hsu , Fei-Jain Wu
IPC分类号： H01L21/56 , H01L21/78 , H01L23/00 , H01L23/31
摘要： A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.

6. 发明申请

US20140120715A1 SEMICONDUCTOR MANUFACTURING METHOD, SEMICONDUCTOR STRUCTURE AND PACKAGE STRUCTURE THEREOF 审中-公开
标题翻译：半导体制造方法，半导体结构及其包装结构
公开(公告)号：US20140120715A1
公开(公告)日：2014-05-01
申请号：US14147891
申请日：2014-01-06
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chih-Ming Kuo , Lung-Hua Ho , Kung-An Lin , Sheng-Hui Chen
IPC分类号： H01L21/768
CPC分类号： H01L21/76885 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13006 , H01L2224/13017 , H01L2224/13023 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13562 , H01L2224/1357 , H01L2224/13644 , H01L2224/16058 , H01L2224/81193 , H01L2924/00014 , H01L2224/05552
摘要： A semiconductor manufacturing method includes providing a carrier having a metallic layer, wherein the metallic layer comprises a plurality of base areas and a plurality of outer lateral areas; forming a first photoresist layer; forming a plurality of bearing portions; removing the first photoresist layer to reveal the bearing portions, each bearing portion comprises a bearing surface having a first area and a second area; forming a second photoresist layer for revealing the first areas of the bearing surfaces; forming a plurality of connection portions, wherein the first areas of the bearing surfaces are covered by the connection portions to make each connection portion connect with each bearing portion to form a snap bump; removing the outer lateral areas of the metallic layer to make the base areas form a plurality of under bump metallurgy layers.
摘要翻译：半导体制造方法包括提供具有金属层的载体，其中所述金属层包括多个基底区域和多个外部横向区域; 形成第一光致抗蚀剂层; 形成多个轴承部; 移除第一光致抗蚀剂层以露出轴承部分，每个轴承部分包括具有第一区域和第二区域的支承表面; 形成用于露出所述支承表面的第一区域的第二光致抗蚀剂层; 形成多个连接部，其中，所述支承面的所述第一区域被所述连接部覆盖，以使每个连接部分与每个支承部分连接以形成卡扣凸块; 去除金属层的外侧面区域，以使基部区域形成多个凸起下的冶金层。

7. 发明申请

US20130213702A1 BUMPING PROCESS AND STRUCTURE THEREOF 有权
标题翻译：保鲜工艺及其结构
公开(公告)号：US20130213702A1
公开(公告)日：2013-08-22
申请号：US13852663
申请日：2013-03-28
申请人： Chipbond Technology Corporation
发明人： Chin-Tang Hsieh , Chih-Ming Kuo
IPC分类号： H05K1/11
CPC分类号： H05K1/111 , H01L21/4846 , H01L23/3192 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0347 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05147 , H01L2224/05541 , H01L2224/05547 , H01L2224/05556 , H01L2224/05557 , H01L2224/05565 , H01L2224/05567 , H01L2224/05578 , H01L2224/05583 , H01L2224/05647 , H01L2224/05655 , H01L2224/05687 , H01L2224/1147 , H01L2224/11912 , H01L2224/13005 , H01L2224/13006 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/13083 , H01L2224/13147 , H01L2224/13155 , H01L2224/13565 , H01L2224/13687 , H01L2924/00014 , H01L2924/301 , H01L2924/384 , Y10T428/12396 , H01L2924/00012 , H01L2924/05042 , H01L2924/05442 , H01L2924/058 , H01L2224/05552
摘要： A bumping process comprises steps of forming a metal layer with copper on a substrate, and the metal layer with copper comprises a plurality of first zones and second zones; forming a photoresist layer on the metal layer with copper; patterning the photoresist layer to form a plurality of openings; forming a plurality of copper bumps within the openings, each of the copper bumps covers the first zones and comprises a first top surface; forming a connection layer on the first top surface; removing the photoresist layer; removing the second zones and enabling each of the first zones to form an under bump metallurgy layer, wherein the under bump metallurgy layer, the copper bump, and the connection layer possess their corresponded peripheral walls, and covering sections of a first protective layer formed on the connection layer may cover those peripheral walls to prevent ionization phenomenon.
摘要翻译：凸起工艺包括在基底上形成具有铜的金属层的步骤，并且具有铜的金属层包括多个第一区域和第二区域; 用铜在金属层上形成光致抗蚀剂层; 图案化光致抗蚀剂层以形成多个开口; 在所述开口内形成多个铜凸块，每个所述铜凸块覆盖所述第一区域并且包括第一顶表面; 在所述第一顶表面上形成连接层; 去除光致抗蚀剂层; 去除所述第二区域并且使得所述第一区域中的每一个形成凸起下冶金层，其中所述凸起下的冶金层，所述铜凸块和所述连接层具有其对应的周壁，以及覆盖在第一区上形成的第一保护层的覆盖部分连接层可以覆盖那些外围壁以防止电离现象。

8. 发明申请

US20130196498A1 BUMPING PROCESS AND STRUCTURE THEREOF 有权
标题翻译：保鲜工艺及其结构
公开(公告)号：US20130196498A1
公开(公告)日：2013-08-01
申请号：US13753936
申请日：2013-01-30
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chih-Ming Kuo , Yie-Chuan Chiu , Lung-Hua Ho
IPC分类号： H01L21/768
CPC分类号： H01L21/76885 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/034 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05184 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/11472 , H01L2224/11903 , H01L2224/13147 , H01L2224/13562 , H01L2224/13564 , H01L2224/13582 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2924/00014 , H01L2224/05552
摘要： A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer.
摘要翻译：碰撞过程包括提供硅衬底; 在硅衬底上形成含钛金属层，所述含钛金属层包括多个第一区域和多个第二区域; 在含钛金属层上形成第一光致抗蚀剂层; 图案化第一光致抗蚀剂层以形成多个第一开口槽; 在第一开口槽内形成多个铜凸块，所述铜凸块包括第一顶表面和第一环表面; 去除第一光致抗蚀剂层; 在含钛金属层上形成第二光致抗蚀剂层; 图案化所述第二光致抗蚀剂层以形成多个第二开口槽; 在空间，第一顶表面和第一环表面处形成多个凸块隔离层; 在凸块隔离层上形成多个连接层; 去除第二光致抗蚀剂层，去除第二区域以形成凸起下的冶金层。

9. 发明申请

US20130181346A1 BUMPING PROCESS AND STRUCTURE THEREOF 审中-公开
标题翻译：保鲜工艺及其结构
公开(公告)号：US20130181346A1
公开(公告)日：2013-07-18
申请号：US13743844
申请日：2013-01-17
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chih-Ming Kuo , Yie-Chuan Chiu , Lung-Hua Ho
IPC分类号： H01L23/498
CPC分类号： H01L23/49811 , H01L24/11 , H01L24/13 , H01L2224/034 , H01L2224/0347 , H01L2224/03912 , H01L2224/0401 , H01L2224/05166 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/11472 , H01L2224/1182 , H01L2224/11906 , H01L2224/13147 , H01L2224/13562 , H01L2224/13564 , H01L2224/13582 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2924/00014 , H01L2924/01074 , H01L2924/01079 , H01L2924/01029 , H01L2924/01028 , H01L2224/05552
摘要： A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots, forming a plurality of bottom coverage layers at the opening slots, proceeding a heat procedure, forming a plurality of external coverage layers to make each of the external coverage layers connect with each of the bottom coverage layers, wherein said external coverage layer and said bottom coverage layer form a wrap layer and completely surround the copper bump, forming a plurality of connective layers on the external coverage layers, removing the photoresist layer, removing the second areas and enabling each of the first areas to form an under bump metallurgy layer.
摘要翻译：凸起工艺包括提供硅衬底，在硅衬底上形成含钛金属层，其中含钛金属层包括多个第一区域和多个第二区域，在含钛金属层上形成光致抗蚀剂层金属层，图案化光致抗蚀剂层以形成多个开口槽，在开口槽处形成多个底部覆盖层，进行热过程，形成多个外部覆盖层，以使每个外部覆盖层与每个的底部覆盖层，其中所述外部覆盖层和所述底部覆盖层形成包裹层并且完全围绕铜凸块，在外部覆盖层上形成多个连接层，去除光致抗蚀剂层，去除第二区域并使能每个第一区域形成凸块下的冶金层。

10. 发明授权

US08772644B2 Carrier with three-dimensional capacitor 有权
标题翻译：载体与三维电容器
公开(公告)号：US08772644B2
公开(公告)日：2014-07-08
申请号：US13644709
申请日：2012-10-04
申请人： Chipbond Technology Corporation
发明人： Chih-Ming Kuo , Lung-Hua Ho , You-Ming Hsu
IPC分类号： H05K1/16
CPC分类号： H01L23/5223 , H01G4/01 , H01L28/86 , H01L2924/0002 , H05K1/162 , H01L2924/00
摘要： A carrier with three-dimensional capacitor includes a substrate and a three-dimensional capacitor, wherein the substrate comprises a trace layer having a first terminal and a second terminal. The three-dimensional capacitor is integrally formed as one piece with the trace layer. The three-dimensional capacitor and the trace layer are made of same material. The three-dimensional capacitor comprises a first capacitance portion and a second capacitance portion, the first capacitance portion comprises a first section, a second section and a first passage, the second capacitance portion is formed at the first passage. The second capacitance portion comprises a third section, a fourth section and a second passage communicated with the first passage. The first capacitance portion is located at the second passage, a first end of the first capacitance portion connects to the first terminal, and a third end of the second capacitance portion connects to the second terminal.
摘要翻译：具有三维电容器的载体包括基板和三维电容器，其中所述基板包括具有第一端子和第二端子的迹线层。三维电容器与轨迹层一体形成。三维电容器和迹线层由相同的材料制成。三维电容器包括第一电容部分和第二电容部分，第一电容部分包括第一部分，第二部分和第一通道，第二电容部分形成在第一通道处。第二电容部分包括与第一通道连通的第三部分，第四部分和第二通道。第一电容部分位于第二通道处，第一电容部分的第一端连接到第一端子，第二电容部分的第三端连接到第二端子。

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