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1. 发明授权

US08962399B2 Method of making a semiconductor layer having at least two different thicknesses 有权
标题翻译：制造具有至少两个不同厚度的半导体层的方法
公开(公告)号：US08962399B2
公开(公告)日：2015-02-24
申请号：US14177593
申请日：2014-02-11
申请人： Commissariat a l'Energie Atomique et aux Ene Alt , STMicroelectronics (Crolles 2) SAS , STMicroelectronics SA
发明人： Maud Vinet , Yves Morand , Heimanu Niebojewski
IPC分类号： H01L21/00 , H01L29/66 , H01L21/02 , H01L21/306 , H01L21/3065 , H01L21/762
CPC分类号： H01L29/66477 , H01L21/02236 , H01L21/02667 , H01L21/30604 , H01L21/3065 , H01L21/7624 , H01L21/76248 , H01L21/76272 , H01L21/76278 , H01L21/84 , H01L27/1207
摘要： A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.
摘要翻译：提供一种用于制造半导体层的半导体层的方法，所述半导体层具有至少两个不同厚度的绝缘体上的半导体层，包括至少一个其上连续设置有绝缘层和第一半导体层的基板，所述方法包括蚀刻第一层使得所述层是连续的并且包括至少一个具有小于至少一个第二区域的厚度的第一区域; 氧化第一层以在其表面上形成电绝缘氧化膜，使得在第一区域中，氧化膜延伸至绝缘层; 部分地除去氧化膜以露出第一区域外的第一层; 在所述堆叠上形成第二半导体层，以与所述第一层形成具有与所述第一和第二区域的厚度不同的厚度的第三连续半导体层。

2. 发明授权

US08980702B2 Method of making a transistor 有权
标题翻译：制造晶体管的方法
公开(公告)号：US08980702B2
公开(公告)日：2015-03-17
申请号：US14177614
申请日：2014-02-11
申请人： Commissariat a l'Energie Atomique et aux ene Alt , STMicroelectronics (Crolles 2) SAS , STMicroelectronics SA
发明人： Heimanu Niebojewski , Yves Morand , Maud Vinet
IPC分类号： H01L21/00 , H01L29/66 , H01L29/78
CPC分类号： H01L29/6656 , H01L21/84 , H01L27/1203 , H01L29/66636 , H01L29/66772 , H01L29/78603
摘要： A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy.
摘要翻译：一种制造晶体管的方法，包括：形成绝缘体上半导体层的叠层，其包括至少一个衬底，其被第一绝缘层和有源层所覆盖以形成晶体管的沟道; 在有源层上形成栅叠层; 产生源极和漏极，包括在栅叠层的任一侧通过至少一个步骤，至少一个步骤，将有源层，第一绝缘层和衬底的一部分选择性地栅极堆叠以形成去除有源层，所述第一绝缘层和位于所述栅叠层下方的所述衬底外部区域的一部分; 在所述基板的裸露表面上形成第二绝缘层，以形成具有所述第一绝缘层的连续绝缘层; 通道的横向端部露出; 并通过外延填充空腔。

3. 发明授权

US09978602B2 Method of making a transistor 有权
公开(公告)号：US09978602B2
公开(公告)日：2018-05-22
申请号：US14923176
申请日：2015-10-26
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT , STMICROELECTRONICS (Crolles 2) SAS , STMICROELECTRONICS SA
发明人： Heimanu Niebojewski , Yves Morand , Maud Vinet
IPC分类号： H01L21/84 , H01L21/28 , H01L29/66 , H01L21/762 , H01L21/02
CPC分类号： H01L21/28123 , H01L21/02532 , H01L21/02538 , H01L21/02645 , H01L21/02667 , H01L21/76205 , H01L21/7624 , H01L21/76248 , H01L21/84 , H01L29/66636 , H01L29/66772 , H01L29/78603
摘要： The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.

4. 发明申请

US20140370666A1 METHOD OF MAKING A SEMICONDUCTOR LAYER HAVING AT LEAST TWO DIFFERENT THICKNESSES 有权
标题翻译：制造具有至少两个不同厚度的半导体层的方法
公开(公告)号：US20140370666A1
公开(公告)日：2014-12-18
申请号：US14177593
申请日：2014-02-11
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT , STMICROELECTRONICS SA , STMICROELECTRONICS (CROLLES 2) SAS
发明人： Maud VINET , Yves Morand , Heimanu Niebojewski
IPC分类号： H01L29/66 , H01L21/762 , H01L21/3065 , H01L21/02 , H01L21/306
CPC分类号： H01L29/66477 , H01L21/02236 , H01L21/02667 , H01L21/30604 , H01L21/3065 , H01L21/7624 , H01L21/76248 , H01L21/76272 , H01L21/76278 , H01L21/84 , H01L27/1207
摘要： A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.
摘要翻译：提供一种用于制造半导体层的半导体层的方法，所述半导体层具有至少两个不同厚度的绝缘体上的半导体层，包括至少一个其上连续设置有绝缘层和第一半导体层的基板，所述方法包括蚀刻第一层使得所述层是连续的并且包括至少一个具有小于至少一个第二区域的厚度的第一区域; 氧化第一层以在其表面上形成电绝缘氧化膜，使得在第一区域中，氧化膜延伸至绝缘层; 部分地除去氧化膜以露出第一区域外的第一层; 在所述堆叠上形成第二半导体层，以与所述第一层形成具有与所述第一和第二区域的厚度不同的厚度的第三连续半导体层。

5. 发明申请

US20140335663A1 METHOD OF MAKING A TRANSITOR 有权
标题翻译：制造传输器的方法
公开(公告)号：US20140335663A1
公开(公告)日：2014-11-13
申请号：US14177614
申请日：2014-02-11
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT , STMICROELECTRONICS SA , STMICROELECTRONICS (CROLLES 2) SAS
发明人： Heimanu NIEBOJEWSKI , Yves Morand , Maud Vinet
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/6656 , H01L21/84 , H01L27/1203 , H01L29/66636 , H01L29/66772 , H01L29/78603
摘要： A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy.
摘要翻译：一种制造晶体管的方法，包括：形成绝缘体上半导体层的叠层，其包括至少一个衬底，其被第一绝缘层和有源层所覆盖以形成晶体管的沟道; 在有源层上形成栅叠层; 产生源极和漏极，包括在栅叠层的任一侧通过至少一个步骤，至少一个步骤，将有源层，第一绝缘层和衬底的一部分选择性地栅极堆叠以形成去除有源层，所述第一绝缘层和位于所述栅叠层下方的所述衬底外部区域的一部分; 在所述基板的裸露表面上形成第二绝缘层，以形成具有所述第一绝缘层的连续绝缘层; 通道的横向端部露出; 并通过外延填充空腔。

6. 发明授权

US09276073B2 Nanowire and planar transistors co-integrated on utbox SOI substrate 有权
公开(公告)号：US09276073B2
公开(公告)日：2016-03-01
申请号：US14266999
申请日：2014-05-01
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT , STMICROELECTRONICS (CROLLES 2) SAS
发明人： Sylvain Barraud , Yves Morand
IPC分类号： H01L21/84 , H01L29/06 , H01L29/41 , H01L51/05 , H01L51/44 , H01L29/786 , H01L27/12
CPC分类号： H01L29/0673 , H01L21/845 , H01L27/1211 , H01L29/0669 , H01L29/413 , H01L29/785 , H01L29/78648 , H01L29/78696 , H01L51/057 , H01L51/444 , H01L2924/13061 , H01L2924/13086
摘要： Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.

7. 发明申请

US20160042955A1 METHOD OF MAKING A TRANSISTOR 有权
标题翻译：制造晶体管的方法
公开(公告)号：US20160042955A1
公开(公告)日：2016-02-11
申请号：US14923176
申请日：2015-10-26
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT , STMICROELECTRONICS (Crolles 2) SAS
发明人： Heimanu NIEBOJEWSKI , Yves Morand , Maud Vinet
IPC分类号： H01L21/28 , H01L21/762 , H01L21/02 , H01L29/66
CPC分类号： H01L21/28123 , H01L21/02532 , H01L21/02538 , H01L21/02645 , H01L21/02667 , H01L21/76205 , H01L21/7624 , H01L21/76248 , H01L21/84 , H01L29/66636 , H01L29/66772 , H01L29/78603
摘要： The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.
摘要翻译：本发明涉及一种晶体管的制造方法，其包括制备绝缘体上半导体层的一叠叠层，其中至少一个衬底上依次配置绝缘层和初始半导体层。该方法包括形成从绝缘层的顶面延伸的至少一个氧化物焊盘，形成由半导体材料制成的附加层，该半导体材料覆盖氧化物焊盘并且旨在形成用于晶体管的沟道，形成栅极堆叠在氧化物垫的上方，并且在栅极堆叠的任一侧上形成源极和漏极。

8. 发明授权

US09899217B2 Method for producing a strained semiconductor on insulator substrate 有权
公开(公告)号：US09899217B2
公开(公告)日：2018-02-20
申请号：US14555897
申请日：2014-11-28
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT , STMICROELECTRONICS SA
发明人： Shay Reboh , Yves Morand , Hubert Moriceau
IPC分类号： H01L21/02 , H01L21/762 , H01L21/84 , H01L29/10 , H01L21/265 , H01L29/786 , H01L27/12 , H01L29/66 , H01L29/78
CPC分类号： H01L21/02689 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02667 , H01L21/02686 , H01L21/26506 , H01L21/7624 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66742 , H01L29/66772 , H01L29/7847 , H01L29/78654 , H01L29/78684
摘要： A method is provided for producing a microelectronic device provided with different strained areas in a superficial layer of a semi-conductor on insulator type substrate, including amorphizing a region of the superficial layer and then a lateral recrystallization of the region from crystalline areas adjoining the region.

9. 发明申请

US20130273722A1 CONTACT ON A HETEROGENEOUS SEMICONDUCTOR SUBSTRATE 有权
标题翻译：在异质半导体基板上接触
公开(公告)号：US20130273722A1
公开(公告)日：2013-10-17
申请号：US13860845
申请日：2013-04-11
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
发明人： Yves Morand , Charles Baudot , Fabrice Nemouchi
IPC分类号： H01L21/02
CPC分类号： H01L21/02381 , H01L21/28518
摘要： A method for producing a microelectronic device with plural zones made of a metal and semiconductor compound, from semiconductor zones made of different semiconductor materials, and on which a thin semiconductor layer is formed prior to the deposition of a metal layer so as to lower the nucleation barrier of the semiconductor zones when reacting with the metal layer.
摘要翻译：一种从由不同半导体材料制成的半导体区域制造具有由金属和半导体化合物制成的多个区域的微电子器件的方法，并且在沉积金属层之前在其上形成薄的半导体层以便降低成核当与金属层反应时半导体区的屏障。

10. 发明授权

US09911820B2 Method for fabrication of a field-effect with reduced stray capacitance 有权
公开(公告)号：US09911820B2
公开(公告)日：2018-03-06
申请号：US15464763
申请日：2017-03-21
申请人： Commissariat a l'energie atomique et aux energies alternatives , STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
发明人： Cyrille Le Royer , Frederic Boeuf , Laurent Grenouillet , Louis Hutin , Yves Morand
IPC分类号： H01L29/06 , H01L29/49 , H01L29/51 , H01L23/535 , H01L29/66 , H01L21/768
CPC分类号： H01L29/4983 , H01L21/76895 , H01L23/535 , H01L29/0649 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66606 , H01L29/66628
摘要： A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

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