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1. 发明申请

US20220157970A1 METHOD FOR FABRICATING A DOPED REGION OF A MICROELECTRONIC DEVICE 有权
公开(公告)号：US20220157970A1
公开(公告)日：2022-05-19
申请号：US17455425
申请日：2021-11-18
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Shay Reboh
IPC分类号： H01L29/66
摘要： A method for forming at least one doped region of a transistor includes providing a stack having an insulating layer, an active layer, and a gate pattern having a first lateral flank and removing a first portion of the active layer not overlaid by the gate pattern and extending down to the gate pattern, at the edge of a second portion of the active layer overlaid by the gate pattern, so as to expose an edge of the second portion. The edge extends substantially in a continuation of the lateral flank of the gate pattern. The method also includes forming a first spacer having an L shape and having a basal portion in contact with the insulating layer and a lateral portion in contact with the lateral flank; forming a second spacer on the first spacer; removing the basal portion of the first spacer by selective etching with respect to the second spacer, so as to expose the edge of the second portion; and forming the doped region by epitaxy from the exposed edge.

2. 发明授权

US10950491B2 Method for transferring a useful layer 有权
公开(公告)号：US10950491B2
公开(公告)日：2021-03-16
申请号：US16324461
申请日：2017-08-01
申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives , Soitec
发明人： Didier Landru , Nadia Ben Mohamed , Oleg Kononchuk , Frederic Mazen , Damien Massy , Shay Reboh , Francois Rieutord
IPC分类号： H01L21/762 , H01L21/324 , H01L21/263
摘要： A useful layer is layered onto a support by a method that includes the steps of forming an embrittlement plane by implanting light elements into a first substrate, so as to form a useful layer between such plane and one surface of the first substrate; applying the support onto the surface of the first substrate so as to form an assembly to be fractured; applying a heat treatment for embrittling the assembly to be fractured; and initiating and propagating a fracture wave into the first substrate along the embrittlement plane. The fracture wave is initiated in a central area of the embrittlement plane and the propagation speed of the wave is controlled so that the velocity thereof is sufficient to cause the interactions of the fracture wave with acoustic vibrations emitted upon the initiation and/or propagation thereof, if any, are confined to a peripheral area of the useful layer.

3. 发明授权

US10256102B2 Method for fabricating a field effect transistor having a surrounding grid 有权
公开(公告)号：US10256102B2
公开(公告)日：2019-04-09
申请号：US15938321
申请日：2018-03-28
申请人： Commissariat a l'energie atomique et aux energies alternatives
发明人： Remi Coquand , Emmanuel Augendre , Shay Reboh
IPC分类号： H01L21/285 , H01L29/66 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/775 , H01L29/06 , H01L29/08 , H01L21/02 , H01L29/45 , H01L29/786
摘要： A process for fabricating a gate-wrap-around field-effect transistor is provided, including providing a substrate surmounted with first and second nanowires extending in a same longitudinal direction and having a median portion covered by a first material, and first and second ends that are arranged on either side of the median portion, a periphery of which is covered by respective first and second dielectric spacers made of a second material that is different from the first material, the ends having exposed lateral faces; doping a portion of the first and second ends via the lateral faces; depositing an amorphous silicon alloy on the first and second lateral faces followed by crystallizing the alloy; and depositing a metal on either side of the nanowires to form first and second metal contacts that respectively make electrical contact with the doped portions of the first and second ends of the nanowires.

4. 发明授权

US10147818B2 Enhanced method of stressing a transistor channel zone 有权
公开(公告)号：US10147818B2
公开(公告)日：2018-12-04
申请号：US14950416
申请日：2015-11-24
申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives
发明人： Shay Reboh , Benoit Mathieu
IPC分类号： H01L29/78 , H01L29/66 , H01L29/51
摘要： A method of straining a transistor channel zone is provided, including a) forming a plurality of stress blocks based on a material having an intrinsic stress, around a zone based on a semiconducting material in which a transistor channel will be made and on which a transistor gate will be formed, the stress blocks inducing a stress in the zone; b) forming a gate block on the zone, the gate block being disposed between the stress blocks; and c) at least partially removing the stress blocks without removing the gate block, wherein the gate block has a Young's modulus and a thickness such that the stress blocks are at least partially removed in step c) and the induced stress is at least partially maintained in the zone after the stress blocks are at least partially removed.

5. 发明授权

US10115590B2 Manufacturing of silicon strained in tension on insulator by amorphisation then recrystallisation 有权
公开(公告)号：US10115590B2
公开(公告)日：2018-10-30
申请号：US15490212
申请日：2017-04-18
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Shay Reboh , Aurore Bonneviaille
IPC分类号： H01L21/266 , H01L21/02 , H01L21/225 , H01L21/265 , H01L21/762 , H01L21/84 , H01L29/78
摘要： Method for making a strained silicon structure, wherein a silicon germanium layer is formed on the silicon layer, followed by another layer with a lower concentration of germanium before selective amorphisation of the silicon and silicon germanium layer relative to this other layer before the assembly is recrystallised so as to strain the silicon semiconducting layer.

6. 发明授权

US09343375B2 Method for manufacturing a transistor in which the strain applied to the channel is increased 有权
标题翻译：制造施加到通道的应变的晶体管的制造方法
公开(公告)号：US09343375B2
公开(公告)日：2016-05-17
申请号：US14802283
申请日：2015-07-17
申请人： Commissariat a L'Energie Atomique et aux Energies Alternatives
发明人： Perrine Batude , Frederic Mazen , Shay Reboh , Benoit Sklenard
IPC分类号： H01L21/8238 , H01L21/84 , H01L29/66
CPC分类号： H01L29/66772 , H01L29/66742 , H01L29/7847 , H01L29/7848 , H01L29/78618 , H01L29/78687 , H01L29/78696
摘要： Method of manufacturing a transistor on a layer made of a first crystalline semiconducting material to make a channel, deposited on a dielectric layer, the method including the following steps: epitaxial growth of zones made of a second semiconducting material on the layer made of a first crystalline semiconducting material, so as to form source and drain blocks with the layer made of a first crystalline semiconducting material on each side of the channel, the second semiconducting material having a lattice parameter different from that of the first semiconducting material, in-depth amorphization of part of zones made of a second semiconducting material so as to keep only one layer of second crystalline semiconducting material on the surface of the source and drain blocks, and amorphization of zones of the layer made of a first semiconducting material located under zones made of a second semiconducting material, recrystallization of the source and drain blocks such that the second semiconducting material imposes its lattice parameter on the source and drain zones.
摘要翻译：在由第一晶体半导体材料制成的层上制造沉积在电介质层上的沟道的晶体管的方法，所述方法包括以下步骤：由第二半导体材料制成的区域在第一晶体半导体材料，以便在通道的每一侧上由第一晶体半导体材料制成的层形成源极和漏极区段，第二半导体材料具有不同于第一半导体材料的晶格参数，深度非晶化的部分由第二半导体材料制成的区域，以便在源极和漏极区域的表面上仅保持一层第二晶体半导体材料，以及由位于由第一半导体材料制成的区域下方的第一半导体材料制成的层的区域的非晶化第二半导体材料，源极和漏极块的再结晶，使得第二半导体材料导电材料在源极和漏极区域施加其晶格参数。

7. 发明授权

US11515148B2 Method for producing at least one device in compressive strained semiconductor 有权
公开(公告)号：US11515148B2
公开(公告)日：2022-11-29
申请号：US16914541
申请日：2020-06-29
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Loic Gaben , Cyrille Le Royer , Fabrice Nemouchi , Nicolas Posseme , Shay Reboh
IPC分类号： H01L21/02 , H01L21/8238 , H01L21/3105
摘要： Method for producing a semiconductor device, including: producing, on a first region of a surface layer comprising a first semiconductor and disposed on a buried dielectric layer, a layer of a second compressive strained semiconductor along a first direction; etching a trench through the layer of the second semiconductor forming an edge of a portion of the layer of the second semiconductor oriented perpendicularly to the first direction, and wherein the bottom wall is formed by the surface layer; thermal oxidation forming in the surface layer a semiconductor compressive strained portion along the first direction and forming in the trench an oxide portion; producing, through the surface layer and/or the oxide portion, and through the buried dielectric layer, dielectric isolation portions around an assembly formed of the compressive strained semiconductor portion and the oxide portion; and wherein the first semiconductor is silicon, the second semiconductor is SiGe, and said at least one compressive strained semiconductor portion includes SiGe.

8. 发明授权

US11469137B2 Manufacturing process of an RF-SOI trapping layer substrate resulting from a crystalline transformation of a buried layer 有权
公开(公告)号：US11469137B2
公开(公告)日：2022-10-11
申请号：US17124184
申请日：2020-12-16
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Shay Reboh , Pablo Acosta Alba , Emmanuel Augendre
IPC分类号： H01L21/762 , H01L21/763 , H01L23/66 , H01L27/12
摘要： A method for manufacturing a semiconductor-on-insulator type substrate for radiofrequency applications is provided, including the steps of: directly bonding a support substrate of a single crystal material and a donor substrate including a thin layer of a semiconductor material, one or more layers of dielectric material being at a bonding interface thereof; transferring the thin layer onto the support substrate; and forming an electric charge trap region in the support substrate in contact with the one or more layers of the dielectric material present at the bonding interface, by transforming a buried zone of the support substrate into a polycrystal.

9. 发明申请

US20210257450A1 CREATION OF STRESS IN THE CHANNEL OF A NANOSHEET TRANSISTOR 有权
公开(公告)号：US20210257450A1
公开(公告)日：2021-08-19
申请号：US17240002
申请日：2021-04-26
申请人： International Business Machines Corporation , COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Nicolas Loubet , Tenko Yamashita , Guillaume Audoit , Nicolas Bernier , Remi Coquand , Shay Reboh
IPC分类号： H01L29/06 , H01L29/78 , H01L29/417
摘要： Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.

10. 发明授权

US10714392B2 Optimizing junctions of gate all around structures with channel pull back 有权
公开(公告)号：US10714392B2
公开(公告)日：2020-07-14
申请号：US16038985
申请日：2018-07-18
申请人： International Business Machines Corporation , COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Nicolas Loubet , Emmanuel Augendre , Remi Coquand , Shay Reboh
IPC分类号： H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/06 , H01L29/78 , H01L29/423 , H01L27/088 , H01L21/3065 , H01L21/306
摘要： Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.

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