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1. 发明授权

US10063305B2 Communications link performance analyzer that accommodates forward error correction 有权
公开(公告)号：US10063305B2
公开(公告)日：2018-08-28
申请号：US15365579
申请日：2016-11-30
申请人： CREDO TECHNOLOGY GROUP LIMITED
发明人： Junqing Sun , Haoli Qian
IPC分类号： H04L7/04 , H04B7/06 , H04L1/16 , H04L12/721 , H04L1/20 , H04L1/24
CPC分类号： H04B7/0632 , H04L1/16 , H04L1/203 , H04L1/242 , H04L1/244 , H04L45/123
摘要： Illustrative communications link performance analyzer methods and modules that accommodate FEC. In at least some embodiments, a method for characterizing communications link performance includes: (A) transmitting a predetermined bit stream across a physical communications link to produce a receive signal; (B) deriving a received bit stream from the receive signal with a receiver, the receiver including an embedded debug module having: (1) a bit counter dividing the received bit stream into symbols and frames; (2) an error counter determining a symbol error count for each frame; and (3) an aggregator obtaining at least one performance-related statistic from the symbol error counts; (C) generating a performance measure based on the at least one performance-related statistic; and (D) displaying a visual representation of the performance measure.

2. 发明授权

US11300613B2 Systems and methods for testing jitter tolerance 有权
公开(公告)号：US11300613B2
公开(公告)日：2022-04-12
申请号：US17022311
申请日：2020-09-16
申请人： Credo Technology Group Limited
发明人： Arshan Aga , Haoli Qian , Junqing Sun , James Bartenslager
IPC分类号： G01R31/317 , G01R29/26
摘要： A method of assessing the ability of one or more multi-die circuit elements to tolerate the presence of jitter in intra-package. The method includes: providing a first die having a set of transmitters for digital communications, the set of transmitters comprising a first transmitter and a second transmitter; providing a second die having a set of receivers for digital communications; providing a performance monitor; coupling, using an intra-package trace, a first transmit signal from the first transmitter to a receiver of the set of receivers; coupling a second transmit signal from the second transmitter to an external pin; supplying an input signal that induces jitter in the first and second transmit signals; measuring jitter in the second transmit signal via the external pin; and determining, using the performance monitor, a performance characteristic of the second die.

3. 发明授权

US11032111B2 Serdes pre-equalizer having adaptable preset coefficient registers 有权
公开(公告)号：US11032111B2
公开(公告)日：2021-06-08
申请号：US16552927
申请日：2019-08-27
申请人： CREDO TECHNOLOGY GROUP LIMITED
发明人： Junqing Sun , Haoli Qian
IPC分类号： H04L25/03 , H04L7/00 , G06N20/00 , H04B1/40
摘要： An illustrative SerDes (serializer-deserializer) communications method embodiment may include a transceiver: selecting one of multiple registers to specify initial pre-equalizer coefficient values; updating the initial pre-equalizer coefficient values during a training phase; and using the updated pre-equalizer coefficient values to convey a transmit data stream. In an illustrative embodiment of a chip-to-module communications link, a port connector couples a port transceiver to a pluggable module transceiver, the pluggable module transceiver including: one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.

4. 发明授权

US10992501B1 Eye monitor for parallelized digital equalizers 有权
公开(公告)号：US10992501B1
公开(公告)日：2021-04-27
申请号：US16836553
申请日：2020-03-31
申请人： CREDO TECHNOLOGY GROUP LIMITED
发明人： Junqing Sun , Haoli Qian
IPC分类号： H04L25/03 , H03L7/081
摘要： An illustrative integrated receiver circuit embodiment includes: a set of analog-to-digital converters that sample a receive signal in response to staggered clock signals to provide a parallel set of sampled receive signals; an equalizer that converts the parallel set of sampled receive signals into a parallel set of equalized signals; one or more quantizers that derives symbol decisions from the parallel set of equalized signals; a digital timing circuit that generates the staggered clock signals based on the parallel set of equalized signals; and a clock skew adjustment circuit that provides a controllable skew of at least one of said staggered clock signals relative to at least one other of the staggered clock signals. A monitor circuit is included to provide a reliability indicator for the symbol decisions, as is a controller that determines a dependence of the reliability indicator on the controllable skew.

5. 发明申请

US20170155440A1 Communications Link Performance Analyzer that Accommodates Forward Error Correction 审中-公开
公开(公告)号：US20170155440A1
公开(公告)日：2017-06-01
申请号：US15365579
申请日：2016-11-30
申请人： CREDO TECHNOLOGY GROUP LIMITED
发明人： Junqing Sun , HAOLI QIAN
IPC分类号： H04B7/06 , H04L12/721 , H04L1/16
CPC分类号： H04B7/0632 , H04L1/16 , H04L1/203 , H04L1/242 , H04L1/244 , H04L45/123
摘要： Illustrative communications link performance analyzer methods and modules that accommodate FEC. In at least some embodiments, a method for characterizing communications link performance includes: (A) transmitting a predetermined bit stream across a physical communications link to produce a receive signal; (B) deriving a received bit stream from the receive signal with a receiver, the receiver including an embedded debug module having: (1) a bit counter dividing the received bit stream into symbols and frames; (2) an error counter determining a symbol error count for each frame; and (3) an aggregator obtaining at least one performance-related statistic from the symbol error counts; (C) generating a performance measure based on the at least one performance-related statistic; and (D) displaying a visual representation of the performance measure.

6. 发明授权

US11038602B1 On-chip jitter evaluation for SerDes 有权
公开(公告)号：US11038602B1
公开(公告)日：2021-06-15
申请号：US16782926
申请日：2020-02-05
申请人： CREDO TECHNOLOGY GROUP LIMITED
发明人： Junqing Sun , Haoli Qian
IPC分类号： H04B17/21 , H04B17/14 , H04L12/28
摘要： An illustrative integrated circuit and method providing on-chip jitter evaluation. One illustrative integrated circuit embodiment includes a digital receiver having a timing recovery circuit that determines a phase offset signal from estimated timing errors of previous sampling instants; and an on-chip memory that captures the phase offset signal, the on-chip memory being coupled to a processor that derives one or more jitter measurements from the phase offset signal. For initial calibration, the processor may configure the receiver for loop back operation, and thereafter the calibration values may enable evaluation of remote transmitter clock jitter.

7. 发明授权

US11005567B2 Efficient multi-mode DFE 有权
公开(公告)号：US11005567B2
公开(公告)日：2021-05-11
申请号：US16459491
申请日：2019-07-01
申请人： CREDO TECHNOLOGY GROUP LIMITED
发明人： Junqing Sun , Haoli Qian
IPC分类号： H04B10/294 , H04B10/58 , H04B10/61 , H04B10/40 , H03H7/30 , H04B1/10 , H04L25/03
摘要： An illustrative SerDes receiver includes: a front-end filter, a precomputation unit, a selection element, and a controller. The front end filter converts a receive signal into a linearly-equalized signal. The precomputation unit accepts the linearly-equalized signal with or without a subtracted feedback signal, and employs a set of comparators with threshold values that depend on a first post-cursor ISI value F1, the set of comparators operating to generate a set of tentative symbol decisions. The selection element derives a selected symbol decision from each set of tentative symbol decisions, thereby deriving a sequence of symbol decisions from the receive signal. The controller constrains F1 if the receive signal uses a PAM4 signal constellation, setting F1 to equal zero if the receive signal is conveyed via a low-loss channel and to equal one if the receive signal is conveyed via a high-loss channel.

8. 发明申请

US20200249714A1 Clock Recovery Using Between-Interval Timing Error Estimation 审中-公开
公开(公告)号：US20200249714A1
公开(公告)日：2020-08-06
申请号：US16269491
申请日：2019-02-06
申请人： CREDO TECHNOLOGY GROUP LIMITED
发明人： Fang CAI , Junqing Sun , Haoli Qian
IPC分类号： G06F1/06 , G06F11/16 , H04L7/027
摘要： Disclosed clock recovery modules provide improved performance with only limited complexity and power requirements. In one illustrative embodiment, a clock recovery method includes: oversampling a receive signal to obtain mid-symbol interval (MSI) samples and between-symbol interval (BSI) samples; processing at least the MSI samples to obtain symbol decisions; filtering the symbol decisions to obtain BSI targets; determining a timing error based on a difference between the BSI samples and the BSI targets; and deriving from the timing error a clock signal for said oversampling.

9. 发明授权

US10447509B1 Precompensator-based quantization for clock recovery 有权
公开(公告)号：US10447509B1
公开(公告)日：2019-10-15
申请号：US16110594
申请日：2018-08-23
申请人： Credo Technology Group Limited
发明人： Fang Cai , Junqing Sun , Haoli Qian
IPC分类号： H04L25/03 , H04B14/02 , H04L27/01
摘要： Precompensator-based quantization techniques offer a way to reduce the complexity and power requirements of clock recovery modules while offering improved timing recovery performance relative to a bang-bang scheme operating in a lossy channel. One illustrative method embodiment includes: (a) obtaining a receive signal having a sequence of symbols from a symbol set, the receive signal exhibiting trailing intersymbol interference; (b) operating on the receive signal with a precompensation unit having a set of comparators to produce, for each sampling instant, a set of comparator results representing a quantized receive signal value, the set of comparators applying a set of threshold values that at least partly compensate for the trailing intersymbol interference; (c) deriving a symbol decision from each set of comparator results; (d) combining the symbol decisions with said quantized receive signal values to determine an estimated timing error for each sampling instant; and (e) filtering the estimated timing errors to generate a sampling clock.

10. 发明授权

US10212260B2 SerDes architecture with a hidden backchannel protocol 有权
公开(公告)号：US10212260B2
公开(公告)日：2019-02-19
申请号：US15654446
申请日：2017-07-19
申请人： Credo Technology Group Limited
发明人： Junqing Sun
IPC分类号： H04L29/00 , H04B10/077 , H04L29/06
摘要： An illustrative multi-lane communication method implements a hidden backchannel to communicate equalization information and/or other link-related data without impinging on the user bandwidth allocated by the relevant articles of IEEE Std 802.3. One embodiment is implemented by a transceiver: (a) receiving signals from different receive channels; (b) converting each receive channel signal into a lane of a multi-lane receive data stream via demodulation and error measurement; (c) deriving outgoing backchannel information based at least in part on the error measurement; (d) detecting alignment markers in each lane of the multi-lane receive data stream; (e) extracting incoming backchannel information from a backchannel field following each alignment marker in at least one lane of the multi-lane receive data stream; and (f) modifying the multi-lane receive data stream to obtain a modified multi-lane receive data stream by replacing backchannel fields with PCS (Physical Coding Sublayer) alignment markers, thereby creating sets of grouped PCS alignment markers in said at least one lane.

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