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1. 发明授权

US08943450B1 Model based analog block coverage system 有权
标题翻译：基于模型的模拟块覆盖系统
公开(公告)号：US08943450B1
公开(公告)日：2015-01-27
申请号：US14052342
申请日：2013-10-11
申请人： Cadence Design Systems, Inc.
发明人： Walter Hartong , Paul Christopher Foster , Jinduo Sun
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5063
摘要： A system, method, and computer program product for automatically providing circuit designers with verification coverage information for analog/mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to assemble a schematic representation of a lower-level circuit design from pre-defined building blocks and various types of connections. Embodiments convert the schematic representation into a behavioral model for rapid simulation. Building blocks in the behavioral circuit have coverage-related terms defined either by the designer or by default, such as input and output value ranges, internal state changes, and state timers and timing-related constraints. Embodiments simulate the behavioral circuit, and determine and tangibly output coverage-related information. Manual and automatic behavioral circuit and stimulus modification can maximize coverage for improved behavioral circuit verification. Corresponding improvements to the underlying circuit may result, along with greatly reduced and better focused design and simulation efforts.
摘要翻译：一种用于自动为电路设计人员提供模拟/混合信号电路设计的验证覆盖信息的系统，方法和计算机程序产品。基于图形用户界面的环境允许电路设计人员从预定义的构建块和各种类型的连接中组装较低级别电路设计的示意图。实施例将示意图转换为用于快速模拟的行为模型。行为电路中的构建块具有由设计者或默认定义的覆盖相关术语，例如输入和输出值范围，内部状态变化以及状态定时器和与时序相关的约束。实施例模拟行为电路，并确定和切实输出覆盖相关信息。手动和自动行为电路和刺激修改可以最大限度地提高行为电路验证的覆盖范围。可能会导致对底层电路的相应改进，同时大大减少和更好地集中设计和模拟工作。

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