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1. 发明申请

US20160351564A1 SEMICONDUCTOR STRUCTURE WITH A SPACER LAYER 有权
标题翻译：具有间隔层的半导体结构
公开(公告)号：US20160351564A1
公开(公告)日：2016-12-01
申请号：US15234405
申请日：2016-08-11
申请人： Cambridge Electronics, Inc.
发明人： Mohamed Azize , Bin Lu , Ling Xia
IPC分类号： H01L27/088 , H01L29/20 , H01L29/205 , H01L29/66 , H01L29/423 , H01L29/40 , H01L29/872 , H01L21/8252 , H01L27/06 , H01L29/778
CPC分类号： H01L29/66704 , H01L21/8252 , H01L27/0605 , H01L27/0883 , H01L29/155 , H01L29/2003 , H01L29/205 , H01L29/41766 , H01L29/4236 , H01L29/432 , H01L29/66462 , H01L29/66621 , H01L29/66734 , H01L29/7787 , H01L29/872
摘要： A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer, a band-offset layer having a wider bandgap than the channel layer, a spacer layer having a narrower bandgap than the band-offset layer, and a cap layer comprising at least two sublayers. Each sublayer is selectively etchable with respect to sublayers immediately below and above, each sublayer comprises a III-N material AlxInyGazN in which 0≦x≦1, 0≦y≦1, and 0≦z≦1, at least one sublayer has a non-zero Ga content, and a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer. Also described are methods for fabricating such semiconductor structures, with gate and/or ohmic recesses formed by selectively removing adjacent layers or sublayers. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.
摘要翻译：公开了用于III-Nitride半导体器件的多层半导体结构，包括沟道层，具有比沟道层宽的带隙的带隙偏移层，具有比带隙偏移层窄的带隙的间隔层，以及包括至少两个子层的覆盖层。每个子层相对于紧下面和上方的子层可选择性地蚀刻，每个子层包括其中0≤x≤1,0≤y≤1且0≤z≤1的III-N材料Al x In y Ga z N，至少一个子层具有非零Ga含量，紧靠在间隔层上方的子层具有比间隔层更宽的带隙。还描述了制造这种半导体结构的方法，其中通过选择性地去除相邻的层或子层形成栅极和/或欧姆凹槽。提高了所得设备的性能，同时提供了设计灵活性来降低生产成本和电路占用空间。

2. 发明授权

US09614069B1 III-Nitride semiconductors with recess regions and methods of manufacture 有权
公开(公告)号：US09614069B1
公开(公告)日：2017-04-04
申请号：US15376826
申请日：2016-12-13
申请人： Cambridge Electronics, Inc.
发明人： Bin Lu , Ling Xia
IPC分类号： H01L21/336 , H01L27/088 , H01L29/778 , H01L29/20 , H01L29/205 , H01L29/66
CPC分类号： H01L29/66462 , H01L29/155 , H01L29/2003 , H01L29/41766 , H01L29/42316 , H01L29/4236 , H01L29/432 , H01L29/7783 , H01L29/7787
摘要： A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer comprising a first III-Nitride material, a barrier layer comprising a second III-Nitride material, a pair of ohmic electrodes disposed in ohmic recesses etched into the barrier layer, a gate electrode disposed in a gate recess etched into the barrier layer, and a filler element. The gate electrode is stepped to form a bottom stem and at least one bottom step within the gate recess. The filler element, comprising an insulating material, is disposed at least below the bottom step of the gate electrode within the gate recess. Also described are methods for fabricating such semiconductor structures. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.

3. 发明申请

US20170018617A1 FIELD-PLATE STRUCTURES FOR SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件的现场板结构
公开(公告)号：US20170018617A1
公开(公告)日：2017-01-19
申请号：US15213054
申请日：2016-07-18
申请人： Cambridge Electronics, Inc.
发明人： Ling Xia , Mohamed Azize , Bin Lu
IPC分类号： H01L29/40 , H01L29/423 , H01L29/861 , H01L29/45 , H01L49/02 , H01L29/20 , H01L29/778
CPC分类号： H01L29/404 , H01L27/0629 , H01L28/40 , H01L28/60 , H01L29/2003 , H01L29/402 , H01L29/405 , H01L29/407 , H01L29/41766 , H01L29/42316 , H01L29/4236 , H01L29/452 , H01L29/454 , H01L29/475 , H01L29/66181 , H01L29/7786 , H01L29/861 , H01L29/94
摘要： Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact. A field-plate dielectric is disposed over the semiconductor substrate. An encapsulating dielectric is disposed over the gate contact, wherein the encapsulating dielectric covers a top surface of the gate contact. The source field plate is disposed over the field-plate dielectric in a field plate region, from which the encapsulating dielectric is absent.
摘要翻译：公开了用于半导体器件中的电场管理的场板结构。场板半导体结构包括半导体衬底，源欧姆接触，漏极欧姆接触和设置在源极欧姆接触和漏极欧姆接触之间的栅极区域上的栅极接触，以及连接到源极的源极场欧姆接触。场致电介质设置在半导体衬底之上。封装电介质设置在栅极触点上方，其中封装电介质覆盖栅极触点的顶表面。源场板在场板区域中设置在场板电介质上，不存在封装电介质。

4. 发明申请

US20160300835A1 SEMICONDUCTOR STRUCTURE AND ETCH TECHNIQUE FOR MONOLITHIC INTEGRATION OF III-N TRANSISTORS 有权
标题翻译：用于III-N晶体管的单晶集成的半导体结构和蚀刻技术
公开(公告)号：US20160300835A1
公开(公告)日：2016-10-13
申请号：US15094985
申请日：2016-04-08
申请人： Cambridge Electronics, Inc.
发明人： Ling Xia , Mohamed Azize , Bin Lu
IPC分类号： H01L27/088 , H01L21/8252 , H01L29/778 , H01L29/423
CPC分类号： H01L29/66704 , H01L21/8252 , H01L27/0605 , H01L27/0883 , H01L29/155 , H01L29/2003 , H01L29/41766 , H01L29/4236 , H01L29/432 , H01L29/66462 , H01L29/66621 , H01L29/66734 , H01L29/7787
摘要： Semiconductor structures are disclosed for monolithically integrating multiple III-N transistors with different threshold voltages on a common substrate. A semiconductor structure includes a cap layer comprising a plurality of selectively etchable sublayers, wherein each sublayer is selectively etchable with respect to the sublayer immediately below, wherein each sublayer comprises a material AlxInyGazN (0≦x, y, z≦1), and wherein at least one selectively etchable sublayer has a non-zero Ga content (0
摘要翻译：公开了半导体结构，用于在公共衬底上将具有不同阈值电压的多个III-N晶体管单片集成。半导体结构包括包含多个可选择性蚀刻的子层的覆盖层，其中每个子层相对于紧下方的子层可选择性地蚀刻，其中每个子层包括材料Al x In y Ga z N（0≤x，y，z≤1），并且其中至少一个可选择性蚀刻的子层具有非零的Ga含量（0

5. 发明授权

US09455342B2 Electric field management for a group III-nitride semiconductor device 有权
标题翻译： III族氮化物半导体器件的电场管理
公开(公告)号：US09455342B2
公开(公告)日：2016-09-27
申请号：US14550730
申请日：2014-11-21
申请人： Cambridge Electronics, Inc.
发明人： Bin Lu , Tomas Palacios , Ling Xia , Mohamed Azize
IPC分类号： H01L29/15 , H01L29/778 , H01L29/40 , H01L29/417 , H01L29/20
CPC分类号： H01L29/7787 , H01L29/0607 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/402 , H01L29/405 , H01L29/41725
摘要： A semiconductor device includes a substrate, a first active layer, a second active layer, at least first and second electrodes, an E-field management layer, and at least one injection electrode. The first active layer is disposed over the substrate. The second active layer is disposed on the first active layer such that a laterally extending conductive channel arises which extends in a lateral direction. The laterally extending conductive channel is located between the first active layer and the second active layer. The first and second electrodes are electrically connected to the first active layer. The E-field management layer, which reduces the electric-field gradients arising in the first and second active layers, is disposed over the second active layer. The injection electrode is electrically connected to the E-field management layer.
摘要翻译：半导体器件包括衬底，第一有源层，第二有源层，至少第一和第二电极，E场管理层和至少一个注入电极。第一有源层设置在衬底上。第二有源层设置在第一有源层上，使得出现沿横向方向延伸的横向延伸的导电通道。横向延伸的导电通道位于第一有源层和第二有源层之间。第一和第二电极电连接到第一有源层。减少在第一和第二有源层中出现的电场梯度的电场管理层设置在第二有源层上。注入电极与E场管理层电连接。

6. 发明授权

US09911817B2 Field-plate structures for semiconductor devices 有权
公开(公告)号：US09911817B2
公开(公告)日：2018-03-06
申请号：US15213054
申请日：2016-07-18
申请人： Cambridge Electronics, Inc.
发明人： Ling Xia , Mohamed Azize , Bin Lu
IPC分类号： H01L29/40 , H01L29/423 , H01L29/86 , H01L49/02 , H01L29/861 , H01L29/778 , H01L29/94 , H01L29/20 , H01L29/45 , H01L29/417 , H01L29/47
CPC分类号： H01L29/404 , H01L27/0629 , H01L28/40 , H01L28/60 , H01L29/2003 , H01L29/402 , H01L29/405 , H01L29/407 , H01L29/41766 , H01L29/42316 , H01L29/4236 , H01L29/452 , H01L29/454 , H01L29/475 , H01L29/66181 , H01L29/7786 , H01L29/861 , H01L29/94
摘要： Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact. A field-plate dielectric is disposed over the semiconductor substrate. An encapsulating dielectric is disposed over the gate contact, wherein the encapsulating dielectric covers a top surface of the gate contact. The source field plate is disposed over the field-plate dielectric in a field plate region, from which the encapsulating dielectric is absent.

7. 发明授权

US09754937B1 Hybrid structure with separate controls 有权
公开(公告)号：US09754937B1
公开(公告)日：2017-09-05
申请号：US15449391
申请日：2017-03-03
申请人： Cambridge Electronics, Inc.
发明人： Bin Lu , Ling Xia
IPC分类号： H01L27/088 , H01L21/336 , H03K17/687 , H01L29/16 , H01L29/78 , H01L29/20 , H01L29/778
CPC分类号： H01L27/0883 , H01L21/8258 , H01L29/155 , H01L29/2003 , H01L29/41766 , H01L29/42316 , H01L29/432 , H01L29/7783 , H01L29/7787 , H01L29/7819 , H03K17/102 , H03K17/284 , H03K17/687 , H03K17/6871 , H03K2017/6875
摘要： A hybrid transistor circuit is disclosed for use in III-Nitride (III-N) semiconductor devices, comprising a Silicon (Si)-based Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Group III-Nitride (III-N)-based Field-Effect Transistor (FET), and a driver unit. A source terminal of the III-N-based FET is connected to a drain terminal of the Si-based MOSFET. The driver unit has at least one input terminal, and two output terminals connected to the gate terminals of the transistors respectively. The hybrid transistor circuit is turned on through the driver unit by switching on the Silicon-based MOSFET first before switching on the III-N-based FET, and is turned off through the driver unit by switching off the III-N-based FET before switching off the Silicon-based MOSFET. Also disclosed are integrated circuit packages and semiconductor structures for forming such hybrid transistor circuits. The resulting hybrid circuit provides power-efficient and robust use of III-Nitride semiconductor devices.

8. 发明申请

US20160365437A1 ELECTRIC FIELD MANAGEMENT FOR A GROUP III-NITRIDE SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20160365437A1
公开(公告)日：2016-12-15
申请号：US15248711
申请日：2016-08-26
申请人： Cambridge Electronics, Inc.
发明人： Bin Lu , Tomas Palacios , Ling Xia , Mohamed Azize
IPC分类号： H01L29/778 , H01L29/40 , H01L29/207 , H01L29/205 , H01L29/06 , H01L29/20
CPC分类号： H01L29/7787 , H01L29/0607 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/402 , H01L29/405 , H01L29/41725
摘要： A semiconductor device includes a substrate, a first active layer, a second active layer, at least first and second electrodes, an E-field management layer, and at least one injection electrode. The first active layer is disposed over the substrate. The second active layer is disposed on the first active layer such that a laterally extending conductive channel arises which extends in a lateral direction. The laterally extending conductive channel is located between the first active layer and the second active layer. The first and second electrodes are electrically connected to the first active layer. The E-field management layer, which reduces the electric-field gradients arising in the first and second active layers, is disposed over the second active layer. The injection electrode is electrically connected to the E-field management layer.

9. 发明授权

US09536984B2 Semiconductor structure with a spacer layer 有权
标题翻译：具有间隔层的半导体结构
公开(公告)号：US09536984B2
公开(公告)日：2017-01-03
申请号：US15234405
申请日：2016-08-11
申请人： Cambridge Electronics, Inc.
发明人： Mohamed Azize , Bin Lu , Ling Xia
IPC分类号： H01L21/336 , H01L27/088 , H01L29/66
CPC分类号： H01L29/66704 , H01L21/8252 , H01L27/0605 , H01L27/0883 , H01L29/155 , H01L29/2003 , H01L29/205 , H01L29/41766 , H01L29/4236 , H01L29/432 , H01L29/66462 , H01L29/66621 , H01L29/66734 , H01L29/7787 , H01L29/872
摘要： A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer, a band-offset layer having a wider bandgap than the channel layer, a spacer layer having a narrower bandgap than the band-offset layer, and a cap layer comprising at least two sublayers. Each sublayer is selectively etchable with respect to sublayers immediately below and above, each sublayer comprises a III-N material AlxInyGazN in which 0≦x≦1, 0≦y≦1, and 0≦z≦1, at least one sublayer has a non-zero Ga content, and a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer. Also described are methods for fabricating such semiconductor structures, with gate and/or ohmic recesses formed by selectively removing adjacent layers or sublayers. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.
摘要翻译：公开了用于III-Nitride半导体器件的多层半导体结构，包括沟道层，具有比沟道层宽的带隙的带隙偏移层，具有比带隙偏移层窄的带隙的间隔层，以及包括至少两个子层的覆盖层。每个子层相对于紧下面和上方的子层可选择性地蚀刻，每个子层包括其中0≤x≤1,0≤y≤1且0≤z≤1的III-N材料Al x In y Ga z N，至少一个子层具有非零Ga含量，紧靠在间隔层上方的子层具有比间隔层更宽的带隙。还描述了制造这种半导体结构的方法，其中通过选择性地去除相邻的层或子层形成栅极和/或欧姆凹槽。提高了所得设备的性能，同时提供了设计灵活性来降低生产成本和电路占用空间。

10. 发明申请

US20150349124A1 TRANSISTOR STRUCTURE HAVING BURIED ISLAND REGIONS 审中-公开
标题翻译：拥有岛屿地区的晶体管结构
公开(公告)号：US20150349124A1
公开(公告)日：2015-12-03
申请号：US14706350
申请日：2015-05-07
申请人： Cambridge Electronics, Inc.
发明人： Bin Lu , Tomas Palacios , Ling Xia , Mohamed Azize
IPC分类号： H01L29/78 , H01L29/20 , H01L29/24 , H01L21/02 , H01L29/861 , H01L29/66 , H01L21/283 , H01L29/16 , H01L29/10
摘要： A semiconductor device such as a transistor includes a source region, a drain region, a semiconductor region, at least one island region and at least one gate region. The semiconductor region is located between the source region and the drain region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The gate region is located between the source region and the drain region covering at least a portion of the island regions.
摘要翻译：诸如晶体管的半导体器件包括源极区，漏极区，半导体区，至少一个岛区和至少一个栅极区。半导体区域位于源极区域和漏极区域之间。岛屿地区位于半导体区域。每个岛区域与选自包括电阻率，掺杂类型，掺杂浓度，应变和材料组成的组的一个或多个特性中的半导体区域不同。栅极区域位于覆盖岛状区域的至少一部分的源极区域和漏极区域之间。

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