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1. 发明申请

US20180373635A1 MANAGING CACHE PARTITIONS BASED ON CACHE USAGE INFORMATION 审中-公开
公开(公告)号：US20180373635A1
公开(公告)日：2018-12-27
申请号：US15631085
申请日：2017-06-23
申请人： Cavium, Inc.
发明人： Shubhendu Sekhar Mukherjee , David Asher , Wilson P. Snyder, II
IPC分类号： G06F12/0846 , G06F12/0864 , G06F12/084
摘要： Partition information includes entries that each include an entity identifier and associated cache configuration information. A controller manages memory requests originating from processor cores, including: comparing at least a portion of an address included in a memory request with tags stored in a cache to determine whether the memory request results in a hit or a miss, and comparing an entity identifier included in the memory request with stored entity identifiers to determine a matched entry. The cache configuration information associated with the entity identifier in a matched entry is updated based at least in part on a hit or miss result. The associated cache configuration information includes cache usage information that tracks usage of the cache by an entity associated with the particular entity identifier, and partition descriptors that each define a different group of one or more of the regions.

2. 发明授权

US10013357B2 Managing memory access requests with prefetch for streams 有权
公开(公告)号：US10013357B2
公开(公告)日：2018-07-03
申请号：US15269072
申请日：2016-09-19
申请人： Cavium, Inc.
发明人： Shubhendu Sekhar Mukherjee , David Albert Carlson , Srilatha Manne
IPC分类号： G06F12/00 , G06F12/0862 , G06F12/0897 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/1016 , G06F2212/6024 , G06F2212/6026
摘要： Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or equal to a size of a single cache line; and determining whether or not a next cache line prefetch request corresponding to a particular memory access request will be made based at least in part on whether or not the particular memory access request matches a strided prefetch result for at least one strided stream, and a history of past next cache line prefetch requests.

3. 发明申请

US20160275016A1 MANAGING ADDRESS-INDEPENDENT PAGE ATTRIBUTES 有权
标题翻译：管理地址独立页属性
公开(公告)号：US20160275016A1
公开(公告)日：2016-09-22
申请号：US14662405
申请日：2015-03-19
申请人： Cavium, Inc.
发明人： Shubhendu Sekhar Mukherjee
IPC分类号： G06F12/10
CPC分类号： G06F12/1054 , G06F9/45558 , G06F12/0802 , G06F12/0897 , G06F2009/45583 , G06F2212/1021 , G06F2212/152 , G06F2212/608 , G06F2212/657
摘要： At least one CPU is configured to run a hypervisor at a first access level and at least one guest operating system at a second access level. At the second access level, translating uses mappings in a first page table; and, at the second access level, class information is determined for a memory page mapped by the first page table based on a classification of virtual addresses. At the first access level, translating uses mappings in a second page table; and, at the first access level, class information is determined for the memory page mapped by the second page table based on a classification of intermediate physical addresses. The class information determined at either access level is independent from certain bits used to indicate addresses. Class information determined at different access levels is processed to determine processed class information for the memory page using a dynamic processing rule.
摘要翻译：至少一个CPU被配置为在第一访问级别运行管理程序，并且在第二访问级别运行至少一个客户机操作系统。在第二访问级别，翻译使用第一页表中的映射; 并且在第二访问级别，基于虚拟地址的分类来确定由第一页表映射的存储器页面的类信息。在第一个访问级别，翻译在第二页表中使用映射; 并且在第一访问级别，基于中间物理地址的分类，确定由第二页表映射的存储器页面的类信息。在任一访问级别确定的类信息与用于指示地址的某些位无关。处理在不同访问级别确定的类信息，以使用动态处理规则确定存储器页面的处理类信息。

4. 发明申请

US20160259689A1 MANAGING REUSE INFORMATION IN CACHES 有权
标题翻译：管理缓存中的重用信息
公开(公告)号：US20160259689A1
公开(公告)日：2016-09-08
申请号：US14638266
申请日：2015-03-04
申请人： Cavium, Inc.
发明人： Shubhendu Sekhar Mukherjee
IPC分类号： G06F11/14 , G06F12/08
CPC分类号： G06F11/1402 , G06F12/0802 , G06F12/0895 , G06F12/1045 , G06F2201/805 , G06F2212/608
摘要： Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor and at least one guest operating system. The managing includes: translating from virtual addresses to intermediate physical addresses; translating from the intermediate physical addresses to physical addresses; determining reuse information for memory pages based on estimated reuse of cache lines of data stored within the memory pages; storing the determined reuse information independently from: (1) any bits used to indicate virtual addresses, (2) any bits used to indicate intermediate physical addresses, and (3) any bits used to indicate physical addresses; and using the stored reuse information to store cache lines in a selected group of multiple groups of cache lines of a first cache.
摘要翻译：使用处理器管理地址转换和缓存，该处理器至少包括一个配置为运行管理程序和至少一个客户机操作系统的CPU。管理包括：从虚拟地址转换为中间物理地址; 从中间物理地址转换为物理地址; 基于存储在存储器页面中的数据的高速缓存行的估计重用来确定存储器页面的重用信息; 存储所确定的重用信息，独立于：（1）用于指示虚拟地址的任何比特，（2）用于指示中间物理地址的任何比特，以及（3）用于指示物理地址的任何比特; 以及使用所存储的重用信息来将高速缓存行存储在所选择的第一高速缓存的多个高速缓存行组中。

5. 发明授权

US09405702B2 Caching TLB translations using a unified page table walker cache 有权
标题翻译：使用统一的页表Walker缓存缓存TLB翻译
公开(公告)号：US09405702B2
公开(公告)日：2016-08-02
申请号：US14541616
申请日：2014-11-14
申请人： Cavium, Inc.
发明人： Shubhendu Sekhar Mukherjee , Mike Bertone , Albert Ma
IPC分类号： G06F12/10 , G06F12/08 , G06F12/12
CPC分类号： G06F12/1027 , G06F12/0833 , G06F12/1009 , G06F12/128 , G06F2212/62 , G06F2212/657 , G06F2212/68 , G06F2212/683
摘要： A core executes memory instructions. A memory management unit (MMU) coupled to the core includes a first cache that stores a plurality of final mappings of a hierarchical page table, a page table walker that traverses levels of the page table to provide intermediate results associated with respective levels for determining the final mappings, and a second cache that stores a limited number of intermediate results provided by the page table walker. The MMU compares a portion of the first virtual address to portions of entries in the second cache, in response to a request from the core to invalidate a first virtual address, based on a match criterion that depends on the level associated with each intermediate result stored in an entry in the second cache, and removes any entries in the second cache that satisfy the match criterion.
摘要翻译：核心执行存储器指令。耦合到核心的存储器管理单元（MMU）包括存储分层页表的多个最终映射的第一高速缓存，遍历页表的级别的页表行进者，以提供与各个级别相关联的中间结果，用于确定最终映射，以及第二缓存，其存储由页表步行器提供的有限数量的中间结果。响应于来自核心的使第一虚拟地址无效的请求，MMU将第一虚拟地址的一部分与第二高速缓存中的条目的部分进行比较，该匹配标准取决于与存储的每个中间结果相关联的级别在第二个缓存中的条目中，并删除第二个缓存中满足匹配条件的任何条目。

6. 发明申请

US20160140042A1 INSTRUCTION CACHE TRANSLATION MANAGEMENT 审中-公开
标题翻译：指令缓存翻译管理
公开(公告)号：US20160140042A1
公开(公告)日：2016-05-19
申请号：US14541826
申请日：2014-11-14
申请人： Cavium, Inc.
发明人： Shubhendu Sekhar Mukherjee
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F12/0891 , G06F12/1063 , G06F2212/1016 , G06F2212/452 , G06F2212/683
摘要： Managing an instruction cache of a processing element, the instruction cache including a plurality of instruction cache entries, each entry including a mapping of a virtual memory address to one or more processor instructions, includes: issuing, at the processing element, a translation lookaside buffer invalidation instruction for invalidating a translation lookaside buffer entry in a translation lookaside buffer, the translation lookaside buffer entry including a mapping from a range of virtual memory addresses to a range of physical memory addresses; causing invalidation of one or more of the instruction cache entries of the plurality of instruction cache entries in response to the translation lookaside buffer invalidation instruction.
摘要翻译：管理处理元件的指令高速缓存，所述指令高速缓存包括多个指令高速缓存条目，每个条目包括虚拟存储器地址与一个或多个处理器指令的映射，包括：在处理元件处发出转换后备缓冲器无效化指令，用于使翻译后备缓冲器中的翻译后备缓冲器条目无效，所述翻译后备缓冲器条目包括从虚拟存储器地址范围到物理存储器地址范围的映射; 导致多个指令高速缓存条目中的一个或多个指令高速缓存条目响应于转换后备缓冲器无效指令而导致无效。

7. 发明申请

US20180293114A1 MANAGING FAIRNESS FOR LOCK AND UNLOCK OPERATIONS USING OPERATION PRIORITIZATION 审中-公开
公开(公告)号：US20180293114A1
公开(公告)日：2018-10-11
申请号：US15697736
申请日：2017-09-07
申请人： Cavium, Inc.
发明人： Shubhendu Sekhar Mukherjee , Isam Wadih Akkawi , David Asher , Michael Bertone , David Albert Carlson , Bradley Dobbie , Richard Eugene Kessler
IPC分类号： G06F9/52
CPC分类号： G06F9/526 , G06F9/524
摘要： Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the particular memory location, or (2) an unlock operation corresponding to a particular lock stored in a particular memory location, releasing the particular lock from the first thread using an associated operation message for accessing the particular memory location. Selected operation messages associated with an unlock operation are prioritized over operation messages associated with a lock operation.

8. 发明申请

US20170286296A1 MANAGING SYNONYMS IN VIRTUAL-ADDRESS CACHES 有权
公开(公告)号：US20170286296A1
公开(公告)日：2017-10-05
申请号：US15088354
申请日：2016-04-01
申请人： Cavium, Inc.
发明人： Shubhendu Sekhar Mukherjee
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0811 , G06F12/0848 , G06F12/0855 , G06F12/0864 , G06F12/0871 , G06F12/1063 , G06F2212/1024 , G06F2212/283 , G06F2212/6032
摘要： A virtual-address cache module receives at least a portion of a virtual address and in response indicates a hit or a miss. A first cache structure stores only memory blocks with virtual addresses that are members of a set of multiple synonym virtual addresses that have all been previously received by the virtual-address cache module during the operating period, where each member of a particular set of multiple synonym virtual addresses translates to a common physical address, and a memory block with the common physical address is stored in at most a single storage location within the first cache structure. A second cache structure stores only memory blocks with virtual addresses that do not have any synonym virtual addresses that have been previously received by the virtual-address cache during the operating period.

9. 发明授权

US09772943B1 Managing synonyms in virtual-address caches 有权
公开(公告)号：US09772943B1
公开(公告)日：2017-09-26
申请号：US15088354
申请日：2016-04-01
申请人： Cavium, Inc.
发明人： Shubhendu Sekhar Mukherjee
IPC分类号： G06F12/08 , G06F12/0811 , G06F12/1045 , G06F12/0864 , G06F12/0846 , G06F12/0871 , G06F12/0855
CPC分类号： G06F12/0811 , G06F12/0848 , G06F12/0855 , G06F12/0864 , G06F12/0871 , G06F12/1063 , G06F2212/1024 , G06F2212/283 , G06F2212/6032
摘要： A virtual-address cache module receives at least a portion of a virtual address and in response indicates a hit or a miss. A first cache structure stores only memory blocks with virtual addresses that are members of a set of multiple synonym virtual addresses that have all been previously received by the virtual-address cache module during the operating period, where each member of a particular set of multiple synonym virtual addresses translates to a common physical address, and a memory block with the common physical address is stored in at most a single storage location within the first cache structure. A second cache structure stores only memory blocks with virtual addresses that do not have any synonym virtual addresses that have been previously received by the virtual-address cache during the operating period.

10. 发明授权

US09720773B2 Managing reuse information in caches 有权
公开(公告)号：US09720773B2
公开(公告)日：2017-08-01
申请号：US14638266
申请日：2015-03-04
申请人： Cavium, Inc.
发明人： Shubhendu Sekhar Mukherjee
IPC分类号： G06F12/00 , G06F11/14 , G06F12/0802
CPC分类号： G06F11/1402 , G06F12/0802 , G06F12/0895 , G06F12/1045 , G06F2201/805 , G06F2212/608
摘要： Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor and at least one guest operating system. The managing includes: translating from virtual addresses to intermediate physical addresses; translating from the intermediate physical addresses to physical addresses; determining reuse information for memory pages based on estimated reuse of cache lines of data stored within the memory pages; storing the determined reuse information independently from: (1) any bits used to indicate virtual addresses, (2) any bits used to indicate intermediate physical addresses, and (3) any bits used to indicate physical addresses; and using the stored reuse information to store cache lines in a selected group of multiple groups of cache lines of a first cache.

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