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1. 发明授权

US07729173B2 Method for testing internal high voltage in nonvolatile semiconductor memory device and related voltage output circuit 失效
标题翻译：用于在非易失性半导体存储器件和相关电压输出电路中测试内部高电压的方法
公开(公告)号：US07729173B2
公开(公告)日：2010-06-01
申请号：US11957808
申请日：2007-12-17
申请人： Chae-Hoon Kim , Dae-Han Kim
发明人： Chae-Hoon Kim , Dae-Han Kim
IPC分类号： G11C11/34 , G11C5/14 , G11C8/00
CPC分类号： G11C16/30 , G11C5/145 , G11C16/04 , G11C27/024 , G11C29/02 , G11C29/021
摘要： In a voltage output circuit of a nonvolatile semiconductor memory device, a high voltage generator generates an internal high voltage, a sampling signal generator generates a sampling signal, and a sample and old circuit samples and holds the internal high voltage in accordance with the sampling signal.
摘要翻译：在非易失性半导体存储器件的电压输出电路中，高电压发生器产生内部高电压，采样信号发生器产生采样信号，采样和旧电路采样并根据采样信号保持内部高电压。

2. 发明授权

US07697340B2 Methods and apparatuses for trimming reference cells in semiconductor memory devices 失效
标题翻译：用于修整半导体存储器件中的参考单元的方法和装置
公开(公告)号：US07697340B2
公开(公告)日：2010-04-13
申请号：US11806587
申请日：2007-06-01
申请人： Chae-Hoon Kim , Dae-Han Kim
发明人： Chae-Hoon Kim , Dae-Han Kim
IPC分类号： G11C11/34
CPC分类号： G11C5/143 , G11C16/20 , G11C29/02 , G11C29/026 , G11C29/028 , G11C29/24 , G11C29/50 , G11C2029/5006
摘要： A method and apparatus for trimming a reference cell in a semiconductor memory device are provided. The method includes generating an internal bias current capable of being trimmed, and trimming the reference cell based on the internal bias current. The semiconductor memory device includes a reference cell in which a reference cell current flows between a drain and a source based on a bias voltage, an internal bias current generator configured to generate an internal bias current capable of being trimmed, and a trimming circuit configured to trim the reference cell based on the internal bias current.
摘要翻译：提供了一种用于修整半导体存储器件中的参考单元的方法和装置。该方法包括产生能够被修整的内部偏置电流，以及基于内部偏置电流来修整参考单元。半导体存储器件包括参考单元，其中参考单元电流基于偏置电压在漏极和源极之间流动;内部偏置电流发生器，被配置为产生能够被修整的内部偏置电流;以及微调电路，其被配置为基于内部偏置电流修整参考单元。

3. 发明申请

US20080137433A1 Methods and apparatuses for trimming reference cells in semiconductor memory devices 失效
标题翻译：用于修整半导体存储器件中的参考单元的方法和装置
公开(公告)号：US20080137433A1
公开(公告)日：2008-06-12
申请号：US11806587
申请日：2007-06-01
申请人： Chae-Hoon Kim , Dae-Han Kim
发明人： Chae-Hoon Kim , Dae-Han Kim
IPC分类号： G11C11/34
CPC分类号： G11C5/143 , G11C16/20 , G11C29/02 , G11C29/026 , G11C29/028 , G11C29/24 , G11C29/50 , G11C2029/5006
摘要： A method and apparatus for trimming a reference cell in a semiconductor memory device are provided. The method includes generating an internal bias current capable of being trimmed, and trimming the reference cell based on the internal bias current. The semiconductor memory device includes a reference cell in which a reference cell current flows between a drain and a source based on a bias voltage, an internal bias current generator configured to generate an internal bias current capable of being trimmed, and a trimming circuit configured to trim the reference cell based on the internal bias current.
摘要翻译：提供了一种用于修整半导体存储器件中的参考单元的方法和装置。该方法包括产生能够被修整的内部偏置电流，以及基于内部偏置电流来修整参考单元。半导体存储器件包括参考单元，其中参考单元电流基于偏置电压在漏极和源极之间流动;内部偏置电流发生器，被配置为产生能够被修整的内部偏置电流;以及微调电路，其被配置为基于内部偏置电流修整参考单元。

4. 发明授权

US07738309B2 Semiconductor memory device having fuse circuits and method of controlling the same 有权
标题翻译：具有熔丝电路的半导体存储器件及其控制方法
公开(公告)号：US07738309B2
公开(公告)日：2010-06-15
申请号：US11946359
申请日：2007-11-28
申请人： Hong-Soo Jeon , Dae-Han Kim
发明人： Hong-Soo Jeon , Dae-Han Kim
IPC分类号： G11C17/18
CPC分类号： G11C16/28
摘要： A non-volatile semiconductor memory device includes a read voltage generating circuit, a flash cell fuse circuit and a row decoder. The read voltage generating circuit generates a read voltage in response to a read enable signal and a trim code. The flash cell fuse circuit generates the trim code in response to a cell selection signal and a fuse word-line enable signal, the fuse word-line enable signal being activated after the read enable signal by a first delay time. The row decoder decodes the read voltage in response to a row address signal to generate a decoded read voltage, and to provide the decoded read voltage to a memory cell array.
摘要翻译：非易失性半导体存储器件包括读电压产生电路，闪存单元熔丝电路和行解码器。读取电压产生电路响应于读取使能信号和修剪码产生读取电压。闪存单元熔丝电路响应于单元选择信号和熔丝字线使能信号而生成修整代码，保险丝字线使能信号在读使能信号之后被激活第一延迟时间。行解码器响应于行地址信号解码读取电压以产生解码的读取电压，并将解码的读取电压提供给存储器单元阵列。

5. 发明授权

US07486573B2 Flash memory device and voltage generating circuit for the same 有权
标题翻译：闪存器件和电压发生电路相同
公开(公告)号：US07486573B2
公开(公告)日：2009-02-03
申请号：US11520803
申请日：2006-09-14
申请人： Hong-Soo Jeon , Dae-Han Kim
发明人： Hong-Soo Jeon , Dae-Han Kim
IPC分类号： G11C5/14
CPC分类号： G11C16/30 , G11C11/5642
摘要： A flash memory device may include a memory cell array. The memory cell array may include a plurality of memory cells. The flash memory device may also include a voltage generator which generates a plurality of constant voltages. The voltage generator may comprise of a plurality of voltage regulators, wherein each voltage regulator is configured to divide a high voltage generated from a charge pump to generate at least two constant voltages having a constant voltage difference therebetween. The plurality of voltage regulators may have independent voltage dividing paths, wherein each path is configured to generate a separate constant voltage.
摘要翻译：闪存器件可以包括存储器单元阵列。存储单元阵列可以包括多个存储单元。闪存器件还可以包括产生多个恒定电压的电压发生器。电压发生器可以包括多个电压调节器，其中每个电压调节器被配置为分离从电荷泵产生的高电压以产生其间具有恒定电压差的至少两个恒定电压。多个电压调节器可以具有独立的分压路径，其中每个路径被配置为产生单独的恒定电压。

6. 发明申请

US20080151635A1 Semiconductor memory devices and a method thereof 有权
标题翻译：半导体存储器件及其方法
公开(公告)号：US20080151635A1
公开(公告)日：2008-06-26
申请号：US11892461
申请日：2007-08-23
申请人： Sang-Kug Park , Dae-Han Kim
发明人： Sang-Kug Park , Dae-Han Kim
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C7/08 , G11C7/14
摘要： Semiconductor memory devices and a method thereof are provided. An example semiconductor memory device may include a control signal generation unit configured to generate a plurality of control signals in response to a bias current, a reference current generation unit configured to generate a reference current in response to the plurality of control signals and a sense amplifier configured to sense and amplify data stored in a given memory cell based on the reference current and a current on a bit line connected to the memory cell. Another example semiconductor memory device may include a memory bank including a plurality of memory cells and a sense amplifier bank including a plurality of sense amplifier units sharing a common line, each of the sense amplifier units including a current source configured to form a current path between the common line and a first voltage supply in response to an enable signal and a gating signal and a sense amplifier configured to sense and amplify data stored in a corresponding memory cell among the plurality of memory cells based on a signal on a bit line connected with the corresponding memory cell and a signal on the common line.
摘要翻译：提供半导体存储器件及其方法。示例性半导体存储器件可以包括：控制信号生成单元，被配置为响应于偏置电流产生多个控制信号;参考电流产生单元，被配置为响应于所述多个控制信号产生参考电流;以及读出放大器被配置为基于所述参考电流和连接到所述存储器单元的位线上的电流来感测和放大存储在给定存储器单元中的数据。另一示例性半导体存储器件可以包括存储器组，其包括多个存储器单元和包括共享公共线的多个读出放大器单元的读出放大器组，每个读出放大器单元包括被配置为形成电流源所述公共线路和第一电压电源响应于使能信号和门控信号，以及读出放大器，被配置为基于与所述多个存储器单元中的位线相关联的信号来感测和放大存储在所述多个存储器单元中的相应存储器单元中的数据相应的存储单元和公共线上的信号。

7. 发明申请

US20070081392A1 Flash memory device and voltage generating circuit for the same 有权
标题翻译：闪存器件和电压发生电路相同
公开(公告)号：US20070081392A1
公开(公告)日：2007-04-12
申请号：US11521479
申请日：2006-09-15
申请人： Sung-Kug Park , Dae-Han Kim
发明人： Sung-Kug Park , Dae-Han Kim
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C11/5621 , G11C16/30
摘要： A flash memory device includes a memory cell array including a plurality of memory cells. The flash memory device also includes a voltage generating circuit which generates a plurality of constant voltages to be applied to the memory cell array, the voltage generating circuit including a plurality of voltage regulators which generate at least two constant voltages, each having a constant voltage difference.
摘要翻译：闪存器件包括包括多个存储单元的存储单元阵列。闪速存储装置还包括产生要施加到存储单元阵列的多个恒定电压的电压产生电路，该电压产生电路包括产生至少两个恒定电压的多个电压调节器，每个恒定电压具有恒定的电压差。

8. 发明授权

US07548466B2 Flash memory device and voltage generating circuit for the same 有权
标题翻译：闪存器件和电压发生电路相同
公开(公告)号：US07548466B2
公开(公告)日：2009-06-16
申请号：US11521479
申请日：2006-09-15
申请人： Sang-Kug Park , Dae-Han Kim
发明人： Sang-Kug Park , Dae-Han Kim
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C11/5621 , G11C16/30
摘要： A flash memory device includes a memory cell array including a plurality of memory cells. The flash memory device also includes a voltage generating circuit which generates a plurality of constant voltages to be applied to the memory cell array, the voltage generating circuit including a plurality of voltage regulators which generate at least two constant voltages, each having a constant voltage difference.
摘要翻译：闪存器件包括包括多个存储单元的存储单元阵列。闪速存储装置还包括产生要施加到存储单元阵列的多个恒定电压的电压产生电路，该电压产生电路包括产生至少两个恒定电压的多个电压调节器，每个恒定电压具有恒定的电压差。

9. 发明申请

US20070053228A1 Flash memory device and voltage generating circuit for the same 有权
标题翻译：闪存器件和电压发生电路相同
公开(公告)号：US20070053228A1
公开(公告)日：2007-03-08
申请号：US11482447
申请日：2006-07-07
申请人： Sang-Wan Nam , Dae-Han Kim
发明人： Sang-Wan Nam , Dae-Han Kim
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C16/08 , G11C16/12
摘要： A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a voltage generating circuit for generating a plurality of constant voltages to be applied to the memory cell array, and a selection circuit for selecting one constant voltage among the plurality of the constant voltages and applying the selected one constant voltage to the memory cell array. The voltage generating circuit discharges a leakage current input by the selection circuit through a voltage division path, which generates the constant voltages.
摘要翻译：一种闪存器件及其电压产生电路。闪存包括配置有多个存储单元的存储单元阵列，用于产生施加到存储单元阵列的多个恒定电压的电压产生电路，以及用于选择多个存储单元中的一个恒定电压的选择电路将所选择的一个恒定电压施加到存储单元阵列。电压产生电路通过分压路径对由选择电路输入的漏电流进行放电，产生恒定电压。

10. 发明申请

US20060126387A1 Multi-level cell memory device and associated read method 有权
标题翻译：多级单元存储器件及相关读取方法
公开(公告)号：US20060126387A1
公开(公告)日：2006-06-15
申请号：US11296476
申请日：2005-12-08
申请人： Dae-Han Kim , Seung-Keun Lee
发明人： Dae-Han Kim , Seung-Keun Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/24
摘要： A NOR flash memory device comprises a memory cell adapted to store at least two bits of data. A read operation is performed on the memory cell by generating a reference current with a first magnitude to detect the value of a most significant bit (MSB) and generating the reference current with a second magnitude to detect the value of a least significant bit (LSB). The respective values of the MSB and the LSB are detected by comparing the first and second reference currents to an amount of current flowing through the memory cell during the read operation. The respective magnitudes of the first and second reference currents are determined by different reference voltages generated by a reference voltage generator.
摘要翻译： NOR闪存器件包括适于存储至少两位数据的存储器单元。通过产生具有第一幅度的参考电流来对存储器单元执行读取操作，以检测最高有效位（MSB）的值并产生具有第二幅度的参考电流以检测最低有效位（LSB）的值）。通过在读取操作期间将第一和第二参考电流与流过存储器单元的电流量进行比较来检测MSB和LSB的相应值。第一和第二参考电流的相应大小由参考电压发生器产生的不同参考电压确定。

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