专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08183092B2 Method of fabricating stacked semiconductor structure 有权
标题翻译：叠层半导体结构的制造方法
公开(公告)号：US08183092B2
公开(公告)日：2012-05-22
申请号：US12829704
申请日：2010-07-02
申请人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L21/00 , H01L21/46
CPC分类号： H01L23/3128 , H01L21/561 , H01L21/565 , H01L23/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49175 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/01033 , H01L2924/15174 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.
摘要翻译：提供了堆叠半导体结构及其制造方法。该方法包括将半导体芯片电连接到第一基板上，在第一基板上安装多个对应于半导体芯片的周边的支撑部件，安装第二基板，该第二基板具有部分被带覆盖的第一表面，经由第二表面与支撑构件上的第一表面相对的第二表面，通过接合线电连接第一和第二基板，在第一基板上形成用于封装半导体芯片的密封剂，支撑构件，第二基板，接合线和具有暴露的顶表面的带，并且移除带以露出第二基板的第一表面并允许电子部件安装在其上。本发明防止回流引起的污染，备有特殊的模具，并消除闪光。

2. 发明申请

US20100267202A1 METHOD OF FABRICATING STACKED SEMICONDUCTOR STRUCTURE 有权
标题翻译：制作堆叠半导体结构的方法
公开(公告)号：US20100267202A1
公开(公告)日：2010-10-21
申请号：US12829704
申请日：2010-07-02
申请人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L21/50
CPC分类号： H01L23/3128 , H01L21/561 , H01L21/565 , H01L23/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49175 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/01033 , H01L2924/15174 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.
摘要翻译：提供了堆叠半导体结构及其制造方法。该方法包括将半导体芯片电连接到第一基板上，在第一基板上安装多个对应于半导体芯片的周边的支撑部件，安装第二基板，该第二基板具有部分被带覆盖的第一表面，经由第二表面与支撑构件上的第一表面相对的第二表面，通过接合线电连接第一和第二基板，在第一基板上形成用于封装半导体芯片的密封剂，支撑构件，第二基板，接合线和具有暴露的顶表面的带，并且移除带以露出第二基板的第一表面并允许电子部件安装在其上。本发明防止回流引起的污染，备有特殊的模具，并消除闪光。

3. 发明授权

US07772685B2 Stacked semiconductor structure and fabrication method thereof 有权
标题翻译：叠层半导体结构及其制造方法
公开(公告)号：US07772685B2
公开(公告)日：2010-08-10
申请号：US11591974
申请日：2006-11-01
申请人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/02
CPC分类号： H01L23/3128 , H01L21/561 , H01L21/565 , H01L23/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49175 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/01033 , H01L2924/15174 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.
摘要翻译：提供了堆叠半导体结构及其制造方法。该方法包括将半导体芯片电连接到第一基板上，在第一基板上安装多个对应于半导体芯片的周边的支撑部件，安装第二基板，该第二基板具有部分被带覆盖的第一表面，经由第二表面与支撑构件上的第一表面相对的第二表面，通过接合线电连接第一和第二基板，在第一基板上形成用于封装半导体芯片的密封剂，支撑构件，第二基板，接合线和具有暴露的顶表面的带，并且移除带以露出第二基板的第一表面并允许电子部件安装在其上。本发明防止回流引起的污染，备有特殊的模具，并消除闪光。

4. 发明申请

US20070181990A1 Stacked semiconductor structure and fabrication method thereof 有权
标题翻译：叠层半导体结构及其制造方法
公开(公告)号：US20070181990A1
公开(公告)日：2007-08-09
申请号：US11591974
申请日：2006-11-01
申请人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Chih-Ming Huang , Han-Ping Pu , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/02 , H01L21/00
CPC分类号： H01L23/3128 , H01L21/561 , H01L21/565 , H01L23/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49175 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/01033 , H01L2924/15174 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.
摘要翻译：提供了堆叠半导体结构及其制造方法。该方法包括将半导体芯片电连接到第一基板上，在第一基板上安装多个对应于半导体芯片的周边的支撑部件，安装第二基板，该第二基板具有部分被带覆盖的第一表面，经由第二表面与支撑构件上的第一表面相对的第二表面，通过接合线电连接第一和第二基板，在第一基板上形成用于封装半导体芯片的密封剂，支撑构件，第二基板，接合线和具有暴露的顶表面的带，并且移除带以露出第二基板的第一表面并允许电子部件安装在其上。本发明防止回流引起的污染，备有特殊的模具，并消除闪光。

5. 发明授权

US07679178B2 Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof 有权
标题翻译：可堆叠半导体器件的半导体封装及其制造方法
公开(公告)号：US07679178B2
公开(公告)日：2010-03-16
申请号：US11974441
申请日：2007-10-12
申请人： Han-Ping Pu , Chien-Ping Huang , Chih-Ming Huang , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Han-Ping Pu , Chien-Ping Huang , Chih-Ming Huang , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/02
CPC分类号： H01L21/568 , H01L23/3128 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/15192 , H01L2924/15311 , H01L2924/16151 , H01L2924/16195 , H01L2924/18161 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor package on which a semiconductor device can be stacked and fabrication method thereof are provided. The fabrication method includes the steps of mounting and electrically connecting at least one semiconductor chip on the substrate, mounting an electrical connecting structure consisting of an upper layer circuit board and a lower layer circuit board on the substrate and electrically connecting the electrical connecting structure to the substrate, where the semiconductor chip is received in a receiving space formed in the electrical connecting structure; forming an encapsulant on the substrate encapsulating the semiconductor chip and the electrical connecting structure, and after the encapsulant is formed, exposing top surface of the upper layer circuit board with a plurality of solder pads from the encapsulant to allow at least one semiconductor device to electrically connect the upper layer circuit board so as to form a stack structure.
摘要翻译：提供半导体器件可堆叠的半导体封装件及其制造方法。该制造方法包括以下步骤：在基板上安装和电连接至少一个半导体芯片，将由上层电路板和下层电路板组成的电连接结构安装在基板上，并将电连接结构电连接到衬底，其中所述半导体芯片被容纳在形成在所述电连接结构中的接收空间中; 在封装半导体芯片和电连接结构的基板上形成密封剂，并且在形成密封剂之后，用来自密封剂的多个焊盘将上层电路板的顶表面曝光，以允许至少一个半导体器件电连接上层电路板，形成堆叠结构。

6. 发明申请

US20070164386A1 Semiconductor device and fabrication method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070164386A1
公开(公告)日：2007-07-19
申请号：US11648045
申请日：2006-12-28
申请人： Cheng-Yi Chang , Chien-Ping Huang , Yu-Po Wang , Chih-Ming Huang , Cheng-Hsu Hsiao
发明人： Cheng-Yi Chang , Chien-Ping Huang , Yu-Po Wang , Chih-Ming Huang , Cheng-Hsu Hsiao
IPC分类号： H01L31/0203 , H01L21/56
CPC分类号： H01L27/14687 , H01L24/97 , H01L27/14618 , H01L2224/48091 , H01L2224/48227 , H01L2224/8592 , H01L2224/97 , H01L2924/01033 , H01L2924/15311 , H01L2924/16195 , H01L2224/85 , H01L2924/00014
摘要： A semiconductor device and the fabrication method thereof are provided. The fabrication method includes providing a substrate module plate having a plurality of substrates; attaching at least one sensor chip to each of the substrates of the substrate module plate; electrically connecting each of the sensor chips to each of the substrates through bonding wires; forming an insulating layer between each sensor chip on the substrate module plate, wherein the height of the insulating layers are not greater than the thickness of the sensor chips so as to prevent flash from the insulating layers from contaminating the sensor chips; forming an adhesive lip on the insulating layer or forming a second insulating layer followed by forming the adhesive layer, wherein the adhesive layer or the second insulating layer is higher than the highest loop-height of the bonding wires; adhering a light transmitting cover to each adhesive layer to cover the sensor chip; and cutting the substrate module plate to separate the substrates to form a plurality of semiconductor devices each integrated with at least one sensor chip. As the adhesive layers are not in contact with the bonding wires, the problems of damaging or breaking the bonding wires can be prevented in the process of adhering the light transmitting cover.
摘要翻译：提供半导体器件及其制造方法。该制造方法包括提供具有多个基板的基板模块板; 将至少一个传感器芯片附接到所述基板模块板的每个基板; 通过接合线将每个传感器芯片电连接到每个基板; 在衬底模块板上的每个传感器芯片之间形成绝缘层，其中绝缘层的高度不大于传感器芯片的厚度，以防止来自绝缘层的闪光污染传感器芯片; 在所述绝缘层上形成粘合剂唇缘或形成第二绝缘层，接着形成所述粘合剂层，其中所述粘合剂层或所述第二绝缘层高于所述接合线的最高环高度; 将透光盖粘附到每个粘合剂层以覆盖传感器芯片; 以及切割所述基板模块板以分离所述基板以形成多个半导体器件，每个半导体器件与至少一个传感器芯片集成。由于粘合层不与接合线接触，所以在粘接透光罩的过程中可以防止损坏或断裂接合线的问题。

7. 发明申请

US20080246142A1 Heat dissipation unit and a semiconductor package that has the heat dissipation unit 审中-公开
标题翻译：散热单元和具有散热单元的半导体封装
公开(公告)号：US20080246142A1
公开(公告)日：2008-10-09
申请号：US12080798
申请日：2008-04-04
申请人： Jeng-Yuan Lai , Chien-Ping Huang , Chih-Ming Huang , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Jeng-Yuan Lai , Chien-Ping Huang , Chih-Ming Huang , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/367
CPC分类号： H01L23/4334 , H01L24/48 , H01L24/49 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2224/73265 , H01L2924/00014 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A heat dissipation unit and a semiconductor package having the same are disclosed. The semiconductor package includes a carrier; an electronic component mounted on and electrically connected to the carrier; a heat dissipation unit, which includes a flat section attached to the electronic component, extension sections connected to the flat section, and a heat dissipation section connected to the extension sections; and an encapsulant encapsulating the electronic component and the heat dissipation unit, wherein stress releasing sections are at least disposed at intersectional corners between the extension sections and the flat section so as to prevent projections from being formed by concentrated stresses in a punching process of the heat dissipation unit, thereby maintaining flatness of the flat section and further preventing circuits of the electronic component from being damaged due to a contact point produced between the electronic component and the flat section in a molding process.
摘要翻译：公开了一种散热单元和具有该散热单元的半导体封装。半导体封装包括载体; 电子部件，其安装在所述载体上并与其电连接; 散热单元，其包括附接到所述电子部件的平坦部分，连接到所述平坦部分的延伸部分和连接到所述延伸部分的散热部分; 以及封装电子部件和散热部的密封剂，其中应力释放部至少设置在延伸部和平坦部之间的交叉角处，以防止在热冲压加工中由于集中应力而形成突起从而保持平坦部分的平坦度，并且进一步防止电子部件的电路在模制过程中由于在电子部件和平坦部分之间产生的接触点而损坏。

8. 发明申请

US20080088011A1 Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof 有权
标题翻译：可堆叠半导体器件的半导体封装及其制造方法
公开(公告)号：US20080088011A1
公开(公告)日：2008-04-17
申请号：US11974441
申请日：2007-10-12
申请人： Han-Ping Hu , Chien-Ping Huang , Chih-Ming Huang , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Han-Ping Hu , Chien-Ping Huang , Chih-Ming Huang , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/49 , H01L21/58
CPC分类号： H01L21/568 , H01L23/3128 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/15192 , H01L2924/15311 , H01L2924/16151 , H01L2924/16195 , H01L2924/18161 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor package on which a semiconductor device can be stacked and fabrication method thereof are provided. The fabrication method includes the steps of mounting and electrically connecting at least one semiconductor chip on the substrate, mounting an electrical connecting structure consisting of an upper layer circuit board and a lower layer circuit board on the substrate and electrically connecting the electrical connecting structure to the substrate, where the semiconductor chip is received in a receiving space formed in the electrical connecting structure; forming an encapsulant on the substrate encapsulating the semiconductor chip and the electrical connecting structure, and after the encapsulant is formed, exposing top surface of the upper layer circuit board with a plurality of solder pads from the encapsulant to allow at least one semiconductor device to electrically connect the upper layer circuit board so as to form a stack structure.
摘要翻译：提供半导体器件可堆叠的半导体封装件及其制造方法。该制造方法包括以下步骤：在基板上安装和电连接至少一个半导体芯片，将由上层电路板和下层电路板组成的电连接结构安装在基板上，并将电连接结构电连接到衬底，其中所述半导体芯片被容纳在形成在所述电连接结构中的接收空间中; 在封装半导体芯片和电连接结构的基板上形成密封剂，并且在形成密封剂之后，用来自密封剂的多个焊盘将上层电路板的顶表面曝光，以允许至少一个半导体器件电连接上层电路板，形成堆叠结构。

9. 发明授权

US08058100B2 Method for fabricating chip scale package structure with metal pads exposed from an encapsulant 有权
标题翻译：用于制造具有从密封剂暴露的金属焊盘的芯片级封装结构的方法
公开(公告)号：US08058100B2
公开(公告)日：2011-11-15
申请号：US12788772
申请日：2010-05-27
申请人： Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L21/60
CPC分类号： H01L21/561 , H01L21/568 , H01L23/3114 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/20 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要： A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures.
摘要翻译：公开了一种芯片级封装结构及其制造方法。该方法包括在载体的预定部分上形成金属垫; 在载体上安装芯片，每个芯片具有焊接到金属焊盘的多个导电凸块; 在载体上形成密封剂以封装芯片和导电凸块; 移除载体以暴露金属垫和甚至具有密封剂表面的金属垫; 在所述密封剂上形成电连接到所述金属焊盘的多个第一导电迹线; 在所述第一导电迹线上施加焊接掩模，以及在所述焊接掩模上形成多个开口以暴露所述第一导电迹线的预定部分; 在所述预定部分上形成多个导电元件; 以及切割所述密封剂以形成多个芯片级封装结构。

10. 发明授权

US07993967B2 Semiconductor package fabrication method 有权
标题翻译：半导体封装制造方法
公开(公告)号：US07993967B2
公开(公告)日：2011-08-09
申请号：US12616834
申请日：2009-11-12
申请人： Yih-Jenn Jiang , Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Yih-Jenn Jiang , Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/3121 , H01L21/561 , H01L21/6835 , H01L24/48 , H01L24/97 , H01L2221/68345 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15747 , H01L2924/181 , H01L2924/18161 , H01L2924/351 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2224/0401 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer. In the present invention, the distance between the semiconductor package and the external device is increased, and thermal stress caused by difference between the thermal expansion coefficients is reduced, so as to enhance the reliability of the product.
摘要翻译：公开了半导体封装和制造方法。制造方法包括在金属载体的一个表面上施加牺牲层，在牺牲层上施加绝缘层，以及在牺牲层和绝缘层中形成通孔以露出金属载体; 在每个通孔中形成导电金属层; 在所述绝缘层上形成图案化电路层，以电连接到所述导电金属层; 将至少一个芯片安装在所述绝缘层上并将所述芯片电连接到所述图案化电路层; 形成密封剂以封装所述芯片和所述图案化电路层; 并且去除金属载体和牺牲层以暴露绝缘层和导电金属层，以允许导电金属层从绝缘层突出。在本发明中，半导体封装和外部器件之间的距离增加，由于热膨胀系数之差导致的热应力降低，从而提高了产品的可靠性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式