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1. 发明申请

US20110233582A1 SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件
公开(公告)号：US20110233582A1
公开(公告)日：2011-09-29
申请号：US12732537
申请日：2010-03-26
申请人： Chih Ching Cheng , Ching Wen Tung
发明人： Chih Ching Cheng , Ching Wen Tung
IPC分类号： H01L33/58 , H01L33/62
CPC分类号： H01L33/20 , H01L33/007 , H01L33/16
摘要： A semiconductor device includes a substrate and an epitaxy layer positioned on the substrate. In one embodiment of the present disclosure, the substrate includes an upper surface and a plurality of bumps positioned on the upper surface, and each of the bumps includes a top plane substantially parallel to the upper surface and a plurality of wall surfaces between the top plane and the upper surface. In one embodiment of the present disclosure, the epitaxy layer has the same crystal orientation on the upper surface of the substrate and the wall surfaces of the bumps to reduce defect density and increase protection from electrostatic discharge.
摘要翻译：半导体器件包括衬底和位于衬底上的外延层。在本公开的一个实施例中，基板包括位于上表面上的上表面和多个凸起，并且每个凸块包括基本上平行于上表面的顶平面和顶平面之间的多个壁面和上表面。在本公开的一个实施例中，外延层在基板的上表面和凸块的壁表面上具有相同的晶体取向，以减少缺陷密度并增加对静电放电的保护。

2. 发明授权

US08258531B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US08258531B2
公开(公告)日：2012-09-04
申请号：US12732537
申请日：2010-03-26
申请人： Chih Ching Cheng , Ching Wen Tung
发明人： Chih Ching Cheng , Ching Wen Tung
IPC分类号： H01L33/00
CPC分类号： H01L33/20 , H01L33/007 , H01L33/16
摘要： A semiconductor device includes a substrate and an epitaxy layer positioned on the substrate. In one embodiment of the present disclosure, the substrate includes an upper surface and a plurality of bumps positioned on the upper surface, and each of the bumps includes a top plane substantially parallel to the upper surface and a plurality of wall surfaces between the top plane and the upper surface. In one embodiment of the present disclosure, the epitaxy layer has the same crystal orientation on the upper surface of the substrate and the wall surfaces of the bumps to reduce defect density and increase protection from electrostatic discharge.
摘要翻译：半导体器件包括衬底和位于衬底上的外延层。在本公开的一个实施例中，基板包括位于上表面上的上表面和多个凸起，并且每个凸块包括基本上平行于上表面的顶平面和顶平面之间的多个壁面和上表面。在本公开的一个实施例中，外延层在基板的上表面和凸块的壁表面上具有相同的晶体取向，以减少缺陷密度并增加对静电放电的保护。

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