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1. 发明申请

US20090298281A1 INTERCONNECT STRUCTURE WITH HIGH LEAKAGE RESISTANCE 审中-公开
标题翻译：具有高耐漏电性的互连结构
公开(公告)号：US20090298281A1
公开(公告)日：2009-12-03
申请号：US12539488
申请日：2009-08-11
申请人： Chih-Chao Yang , Satya V. Nitta
发明人： Chih-Chao Yang , Satya V. Nitta
IPC分类号： H01L21/768
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76877 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is provided in which the conductive feature (i.e., conductive material) is not coplanar with the upper surface of the dielectric material, but instead the conductive material is recessed below an upper surface of the dielectric material. In addition to being recessed below the upper surface of the dielectric material, the conductive material of the interconnect structure is surrounded on all sides (i.e., sidewall surfaces, upper surface and bottom surface) by a diffusion barrier material. Unlike prior art interconnect structures, the barrier material located on the upper surface of the recessed conductive material is located with an opening including the recessed conductive material.
摘要翻译：提供了互连结构，其中导电特征（即，导电材料）不与电介质材料的上表面共面，而是导电材料凹陷在电介质材料的上表面下方。除了凹陷在介电材料的上表面之外，互连结构的导电材料通过扩散阻挡材料在所有侧面（即，侧壁表面，上表面和底表面）上被包围。与现有技术的互连结构不同，位于凹陷导电材料的上表面上的阻挡材料定位成具有包括凹入的导电材料的开口。

2. 发明授权

US07830010B2 Surface treatment for selective metal cap applications 有权
标题翻译：选择性金属帽应用的表面处理
公开(公告)号：US07830010B2
公开(公告)日：2010-11-09
申请号：US12062130
申请日：2008-04-03
申请人： Chih-Chao Yang , Satya V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
发明人： Chih-Chao Yang , Satya V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76835 , H01L21/76849 , H01L21/76885 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal cap formation provides a means for controlling the selective formation of the metal cap directly on the non-recessed surface of a conductive material. That is, the selective formation of the metal cap directly on the non-recessed surface of a conductive material is enhanced since the formation rate of the metal cap on the non-recessed surface of a conductive material is greater than on the hydrophobic surface of the low k dielectric material. It is observed that the hydrophobic surface may be a result of treating a damaged surface of the dielectric material with a silylating agent prior to the selective formation of the noble metal cap or, as a result of forming a hydrophobic polymeric layer on the surface of the dielectric material prior to the selective deposition of the noble metal cap. The hydrophobic polymeric layer typically includes atoms of Si, C and O.
摘要翻译：提供了其中含有贵金属的覆盖层直接存在于嵌入低k电介质材料的导电材料的非凹陷表面上的互连结构。已经确定，在金属盖形成之前通过在低k电介质材料上形成疏水表面提供了一种用于直接控制在导电材料的非凹入表面上选择性形成金属帽的手段。也就是说，直接在导电材料的非凹入表面上选择性地形成金属帽，因为金属帽在导电材料的非凹陷表面上的形成速率大于导电材料的疏水表面上的形成速率低k电介质材料。观察到，疏水性表面可以是在选择性形成贵金属盖之前用甲硅烷基化剂处理电介质材料的损坏表面的结果，或者由于在表面上形成疏水性聚合物层在贵金属盖的选择性沉积之前的介电材料。疏水性聚合物层通常包括Si，C和O的原子。

3. 发明申请

US20090250815A1 SURFACE TREATMENT FOR SELECTIVE METAL CAP APPLICATIONS 有权
标题翻译：选择性金属盖应用的表面处理
公开(公告)号：US20090250815A1
公开(公告)日：2009-10-08
申请号：US12062130
申请日：2008-04-03
申请人： CHIH-CHAO YANG , Satya V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
发明人： CHIH-CHAO YANG , Satya V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76835 , H01L21/76849 , H01L21/76885 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal cap formation provides a means for controlling the selective formation of the metal cap directly on the non-recessed surface of a conductive material. That is, the selective formation of the metal cap directly on the non-recessed surface of a conductive material is enhanced since the formation rate of the metal cap on the non-recessed surface of a conductive material is greater than on the hydrophobic surface of the low k dielectric material. It is observed that the hydrophobic surface may be a result of treating a damaged surface of the dielectric material with a silylating agent prior to the selective formation of the noble metal cap or, as a result of forming a hydrophobic polymeric layer on the surface of the dielectric material prior to the selective deposition of the noble metal cap. The hydrophobic polymeric layer typically includes atoms of Si, C and O.
摘要翻译：提供了其中含有贵金属的覆盖层直接存在于嵌入低k电介质材料的导电材料的非凹陷表面上的互连结构。已经确定，在金属盖形成之前通过在低k电介质材料上形成疏水表面提供了一种用于直接控制在导电材料的非凹入表面上选择性形成金属帽的手段。也就是说，直接在导电材料的非凹入表面上选择性地形成金属帽，因为金属帽在导电材料的非凹陷表面上的形成速率大于导电材料的疏水表面上的形成速率低k电介质材料。观察到，疏水性表面可以是在选择性形成贵金属盖之前用甲硅烷基化剂处理电介质材料的损坏表面的结果，或者由于在表面上形成疏水性聚合物层在贵金属盖的选择性沉积之前的介电材料。疏水性聚合物层通常包括Si，C和O的原子。

4. 发明授权

US08034710B2 Bilayer metal capping layer for interconnect applications 失效
标题翻译：用于互连应用的双层金属覆盖层
公开(公告)号：US08034710B2
公开(公告)日：2011-10-11
申请号：US12901176
申请日：2010-10-08
申请人： Chih-Chao Yang , Satya V. Nitta
发明人： Chih-Chao Yang , Satya V. Nitta
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76805 , H01L21/76814 , H01L21/76843 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer is located on a surface of a first metallic cap layer which is, in turn, located on a surface of the conductive feature embedded within a first dielectric material. Both the first and second metallic capping layers are located beneath an opening, e.g., a via opening, the is present within an overlying second dielectric material. The second metallic capping layer protects the first dielectric capping layer from being removed (either completely or partially) during subsequent processing steps. Interconnect structures including via gouging features as well as non-via gouging features are disclosed. The present invention provides methods of fabricating such semiconductor interconnect structures.
摘要翻译：本发明提供了具有改进的可靠性和技术可扩展性的半导体互连结构。在本发明中，第二金属覆盖层位于第一金属覆盖层的表面上，第一金属覆盖层又位于第一电介质材料中的导电特征的表面上。第一和第二金属覆盖层都位于开口下方，例如通孔开口处，存在于覆盖的第二介电材料内。第二金属覆盖层保护第一介电覆盖层在随后的处理步骤期间被去除（完全或部分地）。公开了包括通过气刨特征以及非通孔气刨功能的互连结构。本发明提供制造这种半导体互连结构的方法。

5. 发明申请

US20110024909A1 BILAYER METAL CAPPING LAYER FOR INTERCONNECT APPLICATIONS 失效
标题翻译：双层金属覆盖层用于互连应用
公开(公告)号：US20110024909A1
公开(公告)日：2011-02-03
申请号：US12901176
申请日：2010-10-08
申请人： Chih-Chao Yang , Satya V. Nitta
发明人： Chih-Chao Yang , Satya V. Nitta
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76849 , H01L21/76805 , H01L21/76814 , H01L21/76843 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer is located on a surface of a first metallic cap layer which is, in turn, located on a surface of the conductive feature embedded within a first dielectric material. Both the first and second metallic capping layers are located beneath an opening, e.g., a via opening, the is present within an overlying second dielectric material. The second metallic capping layer protects the first dielectric capping layer from being removed (either completely or partially) during subsequent processing steps. Interconnect structures including via gouging features as well as non-via gouging features are disclosed. The present invention provides methods of fabricating such semiconductor interconnect structures.
摘要翻译：本发明提供了具有改进的可靠性和技术可扩展性的半导体互连结构。在本发明中，第二金属覆盖层位于第一金属覆盖层的表面上，第一金属覆盖层又位于第一电介质材料中的导电特征的表面上。第一和第二金属覆盖层都位于开口下方，例如通孔开口处，存在于覆盖的第二介电材料内。第二金属覆盖层保护第一介电覆盖层在随后的处理步骤期间被去除（完全或部分地）。公开了包括通过气刨特征以及非通孔气刨功能的互连结构。本发明提供制造这种半导体互连结构的方法。

6. 发明授权

US07834457B2 Bilayer metal capping layer for interconnect applications 失效
标题翻译：用于互连应用的双层金属覆盖层
公开(公告)号：US07834457B2
公开(公告)日：2010-11-16
申请号：US12039280
申请日：2008-02-28
申请人： Chih-Chao Yang , Satya V. Nitta
发明人： Chih-Chao Yang , Satya V. Nitta
IPC分类号： H01L21/768
CPC分类号： H01L21/76849 , H01L21/76805 , H01L21/76814 , H01L21/76843 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer is located on a surface of a first metallic cap layer which is, in turn, located on a surface of the conductive feature embedded within a first dielectric material. Both the first and second metallic capping layers are located beneath an opening, e.g., a via opening, the is present within an overlying second dielectric material. The second metallic capping layer protects the first dielectric capping layer from being removed (either completely or partially) during subsequent processing steps. Interconnect structures including via gouging features as well as non-via gouging features are disclosed. The present invention provides methods of fabricating such semiconductor interconnect structures.
摘要翻译：本发明提供了具有改进的可靠性和技术可扩展性的半导体互连结构。在本发明中，第二金属覆盖层位于第一金属覆盖层的表面上，第一金属覆盖层又位于第一电介质材料中的导电特征的表面上。第一和第二金属覆盖层都位于开口下方，例如通孔开口处，存在于覆盖的第二介电材料内。第二金属覆盖层保护第一介电覆盖层在随后的处理步骤期间被去除（完全或部分地）。公开了包括通过气刨特征以及非通孔气刨功能的互连结构。本发明提供制造这种半导体互连结构的方法。

7. 发明申请

US20090218691A1 BILAYER METAL CAPPING LAYER FOR INTERCONNECT APPLICATIONS 失效
标题翻译：双层金属覆盖层用于互连应用
公开(公告)号：US20090218691A1
公开(公告)日：2009-09-03
申请号：US12039280
申请日：2008-02-28
申请人： Chih-Chao Yang , Satya V. Nitta
发明人： Chih-Chao Yang , Satya V. Nitta
IPC分类号： H01L21/768 , H01L23/538
CPC分类号： H01L21/76849 , H01L21/76805 , H01L21/76814 , H01L21/76843 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer is located on a surface of a first metallic cap layer which is, in turn, located on a surface of the conductive feature embedded within a first dielectric material. Both the first and second metallic capping layers are located beneath an opening, e.g., a via opening, the is present within an overlying second dielectric material. The second metallic capping layer protects the first dielectric capping layer from being removed (either completely or partially) during subsequent processing steps. Interconnect structures including via gouging features as well as non-via gouging features are disclosed. The present invention provides methods of fabricating such semiconductor interconnect structures.
摘要翻译：本发明提供了具有改进的可靠性和技术可扩展性的半导体互连结构。在本发明中，第二金属覆盖层位于第一金属覆盖层的表面上，第一金属覆盖层又位于第一电介质材料中的导电特征的表面上。第一和第二金属覆盖层都位于开口下方，例如通孔开口处，存在于覆盖的第二介电材料内。第二金属覆盖层保护第一介电覆盖层在随后的处理步骤期间被去除（完全或部分地）。公开了包括通过气刨特征以及非通孔气刨功能的互连结构。本发明提供制造这种半导体互连结构的方法。

8. 发明申请

US20090200668A1 INTERCONNECT STRUCTURE WITH HIGH LEAKAGE RESISTANCE 审中-公开
公开(公告)号：US20090200668A1
公开(公告)日：2009-08-13
申请号：US12027677
申请日：2008-02-07
申请人： Chih-Chao Yang , Satya V. Nitta
发明人： Chih-Chao Yang , Satya V. Nitta
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76877 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is provided in which the conductive feature (i.e., conductive material) is not coplanar with the upper surface of the dielectric material, but instead the conductive material is recessed below an upper surface of the dielectric material. In addition to being recessed below the upper surface of the dielectric material, the conductive material of the interconnect structure is surrounded on all sides (i.e., sidewall surfaces, upper surface and bottom surface) by a diffusion barrier material. Unlike prior art interconnect structures, the barrier material located on the upper surface of the recessed conductive material is located with an opening including the recessed conductive material.

9. 发明授权

US08481423B2 Methods to mitigate plasma damage in organosilicate dielectrics 失效
公开(公告)号：US08481423B2
公开(公告)日：2013-07-09
申请号：US11857760
申请日：2007-09-19
申请人： John C. Arnold , Griselda Bonilla , William J. Cote , Geraud Dubois , Daniel C. Edelstein , Alfred Grill , Elbert Huang , Robert D. Miller , Satya V. Nitta , Sampath Purushothaman , E. Todd Ryan , Muthumanickam Sankarapandian , Terry A. Spooner , Willi Volksen
发明人： John C. Arnold , Griselda Bonilla , William J. Cote , Geraud Dubois , Daniel C. Edelstein , Alfred Grill , Elbert Huang , Robert D. Miller , Satya V. Nitta , Sampath Purushothaman , E. Todd Ryan , Muthumanickam Sankarapandian , Terry A. Spooner , Willi Volksen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/02063 , H01L21/02126 , H01L21/02203 , H01L21/02274 , H01L21/02304 , H01L21/02348 , H01L21/02362 , H01L21/31138 , H01L21/31144 , H01L21/31633 , H01L21/76814 , H01L21/76826 , H01L21/76831
摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

10. 发明申请

US20110020753A1 Method for reversing tone of patterns on integrated circuit and patterning sub-lithography trenches 审中-公开
标题翻译：用于在集成电路上反转图案色调和图案化亚光刻沟槽的方法
公开(公告)号：US20110020753A1
公开(公告)日：2011-01-27
申请号：US12510001
申请日：2009-07-27
申请人： Lawrence A. Clevenger , Maxime Darnon , Anthony D. Lisi , Satya V. Nitta
发明人： Lawrence A. Clevenger , Maxime Darnon , Anthony D. Lisi , Satya V. Nitta
IPC分类号： G03F7/20
CPC分类号： G03F7/091 , G03F7/40 , H01L21/3086
摘要： A method for reversing the tone of a lithographic image on a substrate comprises depositing a modifiable material on a substrate; applying a photolithographic material on the modifiable material: defining a removable patterned area in the photolithopgraphic material by photolithograpic means; removing the patterned area to produce an exposed region in the modifiable material that substantially conforms to the patterned area; producing a reacted modifiable material by increasing the etch resistance of the modifable material substantially throughout the exposed region so that the etch resistance of the exposed region comprises a region that substantially conforms to the exposed region; and removing the photoresist and the modifiable material to leave the reacted modifiable material and substrate.
摘要翻译：用于反转基底上的平版印刷图像的色调的方法包括将可修改材料沉积在基底上; 将光刻材料施加在可修改的材料上：通过光刻手段在光致剪切材料中限定可移除的图案区域; 去除所述图案化区域以在所述可修改材料中产生基本上符合所述图案化区域的暴露区域; 通过增加可修饰材料的基本上在整个曝光区域的耐蚀刻性而产生可反应的可修饰材料，使得暴露区域的耐蚀刻性包括基本上符合曝光区域的区域; 并除去光致抗蚀剂和可修改的材料以留下可反应的可修改的材料和基材。

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