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1. 发明申请

US20080263493A1 Method and Apparatus for Tie Net Routing 审中-公开
标题翻译：铁网路由方法与装置
公开(公告)号：US20080263493A1
公开(公告)日：2008-10-23
申请号：US11737280
申请日：2007-04-19
申请人： Christopher J Berry , Alan Wagstaff
发明人： Christopher J Berry , Alan Wagstaff
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/78
摘要： A method of performing tie net routing within an integrated circuit chip is disclosed without using wiring. Due to repeated use of designs in modern chip, there are often unused portions of the design that need to be connected permanently to a local logical1 or logical 0. These connections, known as tie nets, are not timing critical signals that, when poorly implemented can get in the way of functional signals in an integrated circuit. The current method is to connect the pin to the nearest power connections of the correct polarity. This requires some amount of wiring resources that may be needed for other functions or pin access. Accordingly, the present invention avoids this situation by avoiding wiring.
摘要翻译：在不使用布线的情况下公开了在集成电路芯片内执行连接网路由的方法。由于在现代芯片中重复使用设计，通常设计中未使用的部分需要永久连接到本地逻辑1或逻辑0。这些连接称为连接网络不是时序关键信号，当执行不良时可以阻碍集成电路中的功能信号。目前的方法是将引脚连接到正确极性的最近的电源连接。这需要一些其他功能或引脚访问可能需要的接线资源。因此，本发明通过避免布线来避免这种情况。

2. 发明申请

US20060200783A1 Decoupling capacitance analysis method 失效
公开(公告)号：US20060200783A1
公开(公告)日：2006-09-07
申请号：US11408228
申请日：2006-04-20
申请人： Christopher Berry , Howard Smith , Richard Underwood , Alan Wagstaff
发明人： Christopher Berry , Howard Smith , Richard Underwood , Alan Wagstaff
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.

3. 发明申请

US20060190877A1 Decoupling capacitance analysis method 有权
标题翻译：去耦电容分析方法
公开(公告)号：US20060190877A1
公开(公告)日：2006-08-24
申请号：US11408217
申请日：2006-04-20
申请人： Christopher Berry , Howard Smith , Richard Underwood , Alan Wagstaff
发明人： Christopher Berry , Howard Smith , Richard Underwood , Alan Wagstaff
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.
摘要翻译：用于去耦电容分析的这种方法改进了现有技术，以试图在保持运行时可比性的同时更准确地表示芯片上的电源波动。该方法采用以下技术; a）通过层级降级并将设计划分为可变尺寸网格的方法; b）确定设计的哪些网格位置对于该网格位置中的所有设备没有足够的去耦电容器的算法; c）确定哪些网格位置受到有害的相邻影响的算法; 以及d）以图形方式显示计算结果的方法，以便容易地识别问题区域。

4. 发明申请

US20060047251A1 Medical small-bore tubing system and kit 审中-公开
标题翻译：医用小口径管道系统和套件
公开(公告)号：US20060047251A1
公开(公告)日：2006-03-02
申请号：US10532772
申请日：2003-10-22
申请人： Philip Bickford Smith , Alan Wagstaff
发明人： Philip Bickford Smith , Alan Wagstaff
IPC分类号： A61M5/31
CPC分类号： A61M39/10 , A61M5/3145 , A61M5/344 , A61M5/347 , A61M2039/1033 , A61M2039/1077 , A61M2039/1094 , A61M2205/6045 , A61M2205/6081
摘要： A small bore tubing system employs affordance to assist distinction between different applications of medical tubing and their interconnections, as well as unique keying to avoid misconnection between tubing of different applications. Said affordance is by shape of a grip on connectors of the system, which shapes provide both visual and tactile application-specific affordance (eg. spine and ribs to indicate neuraxial application). Further mechanism affordance ensures appropriate connection mechanism is employed. A kit of components of a medical small-bore tubing connection system has a first converter (14), a second converter (30), a syringe (10) and a needle (50). Each converter (14, 30) has a through bore, a standard female (16) and male (36) connector, and a “different” male (18) and female (32) connector element. The first converter (14) has a latching mechanism (control ring) (20) on the different male connector (18) and which is adapted to engage a flange (34) of the corresponding female connector. Said standard connectors are 6% luer connectors. To the standard outlet of the syringe is permanently secured a first converter (14′). The hypodermic needle has said different female connector (32′) formed directly thereon. The control ring comprises a threaded (26) collar and said flange comprises thread elements (34). The control ring is axially slidable between limits (22, 24), and is rotatably free, on the first converter.
摘要翻译：小口径管道系统采用提供帮助来区分医疗管道及其互连的不同应用，以及独特的键控，以避免不同应用的管道之间的错误连接。所述可用性通过在系统的连接器上的握持的形状，这些形状提供视觉和触觉的应用特定的能力（例如，脊柱和肋条来指示神经轴应用）。进一步的机制可以确保采用适当的连接机制。医疗小口径管道连接系统的组件套件具有第一转换器（14），第二转换器（30），注射器（10）和针（50）。每个转换器（14,30）具有通孔，标准母头（16）和阳（36）连接器以及“不同”的阳（18）和阴（32）连接器元件。第一转换器（14）在不同的公连接器（18）上具有锁定机构（控制环）（20），并且适于接合相应的母连接器的凸缘（34）。所述标准连接器为6％路厄连接器。注射器的标准出口永久地固定在第一转换器（14'）上。皮下注射针具有直接在其上形成的不同的母连接器（32'）。控制环包括螺纹（26）轴环，所述凸缘包括螺纹元件（34）。控制环可在限制（22,24）之间轴向滑动，并且在第一转换器上可旋转自由。

5. 发明申请

US20050228910A1 Method for providing an area optimized binary orthogonality checker 失效
标题翻译：提供区域优化二进制正交检验器的方法
公开(公告)号：US20050228910A1
公开(公告)日：2005-10-13
申请号：US10817279
申请日：2004-04-02
申请人： Patrick Meaney , Alan Wagstaff
发明人： Patrick Meaney , Alan Wagstaff
IPC分类号： G03C1/52 , G06F17/50
CPC分类号： G06F17/5045
摘要： A method for minimizing the area of a binary orthogonality checker implemented in static CMOS circuits for minimizing the gate count and area needed for checker implementation. The method is adaptable to various libraries of logical gates to implement the circuit and the area for each gate in the library. The optimal mix of hierarchical levels and stages is determined such that the orthogonality checker achieves the minimized circuit area. An orthogonality checker is employed in a scalable selector system for controlling data transfers and routing in a data processing system to allow. Combining orthogonality checking with existing selector hierarchically allows for the maximum reuse of circuits, signals, and proximity; thus potentially reducing wiring as well. Multiple hierarchical checks are used in favor of one large. This structure is extended to multiple hierarchical levels and works with orthogonality checks of any size or implementation. The invention also determines the optimal hierarchical structure for a given technology library and a given number of inputs to check. It can also be used within a flat hierarchy or macro as a technique to reduce circuits.
摘要翻译：一种用于最小化在静态CMOS电路中实现的二进制正交检验器的面积的方法，用于最小化检验器实现所需的门数和面积。该方法适用于逻辑门的各种库，以实现库中每个门的电路和区域。确定层次级别和级别的最佳组合，使得正交检验器实现最小化的电路面积。在可扩展选择器系统中采用正交检验器，用于在数据处理系统中控制数据传输和路由以允许。将正交检查与现有选择器分层组合允许电路，信号和接近度的最大重用; 从而潜在地减少布线。使用多层次检查有利于一个大型。该结构扩展到多个层次级别，并且可以与任何大小或实现的正交性检查一起工作。本发明还确定给定技术库的最优层次结构以及给定数量的输入以进行检查。它也可以在平面层级或宏中用作减少电路的技术。

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