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1. 发明授权

US07769986B2 Method and apparatus for register renaming 失效
标题翻译：用于注册重命名的方法和装置
公开(公告)号：US07769986B2
公开(公告)日：2010-08-03
申请号：US11742905
申请日：2007-05-01
申请人： Christopher Michael Abernathy , William Elton Burky , Jens Leenstra , Nicolas Maeding
发明人： Christopher Michael Abernathy , William Elton Burky , Jens Leenstra , Nicolas Maeding
IPC分类号： G06F12/00
CPC分类号： G06F9/3836 , G06F9/3804 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for register renaming are provides in the illustrative embodiments. A mapper receives a request for a data in a logical register. The mapper searches an in-flight map table and a set of architected map tables for the data in the logical register. The mapper identifies an entry in one of the in-flight map table and an architected map table in the set of architected map tables that corresponds with the logical register in the request. The mapper returns a location of a physical register, which holds the requested data.
摘要翻译：在说明性实施例中提供了用于寄存器重命名的方法和装置。映射器接收对逻辑寄存器中的数据的请求。映射器搜索逻辑寄存器中的数据的飞行中地图表和一组架构图。映射器在飞行中的映射表之一中标识一个条目，并在与该请求中的逻辑寄存器对应的一组架构映射表中的架构映射表中。映射器返回一个物理寄存器的位置，它保存所请求的数据。

2. 发明申请

US20080276076A1 METHOD AND APPARATUS FOR REGISTER RENAMING 失效
标题翻译：用于注册的方法和装置
公开(公告)号：US20080276076A1
公开(公告)日：2008-11-06
申请号：US11742905
申请日：2007-05-01
申请人： Christopher Michael Abernathy , William Elton Burky , Jens Leenstra , Nicolas Maeding
发明人： Christopher Michael Abernathy , William Elton Burky , Jens Leenstra , Nicolas Maeding
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3804 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for register renaming are provides in the illustrative embodiments. A mapper receives a request for a data in a logical register. The mapper searches an in-flight map table and a set of architected map tables for the data in the logical register. The mapper identifies an entry in one of the in-flight map table and an architected map table in the set of architected map tables that corresponds with the logical register in the request. The mapper returns a location of a physical register, which holds the requested data.
摘要翻译：在说明性实施例中提供了用于寄存器重命名的方法和装置。映射器接收对逻辑寄存器中的数据的请求。映射器搜索逻辑寄存器中的数据的飞行中地图表和一组架构图。映射器在飞行中的映射表之一中标识一个条目，并在与该请求中的逻辑寄存器对应的一组架构映射表中的架构映射表中。映射器返回一个物理寄存器的位置，它保存所请求的数据。

3. 发明授权

US07962538B2 Method of operand width reduction to enable usage of narrower saturation adder 失效
标题翻译：操作数宽度缩减方法可以使用较窄的饱和加法器
公开(公告)号：US07962538B2
公开(公告)日：2011-06-14
申请号：US11560165
申请日：2006-11-15
申请人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Kerstin Schelm
发明人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Kerstin Schelm
IPC分类号： G06F7/00 , G06F15/00 , G06F7/50 , G06F7/38
CPC分类号： G06F7/49921
摘要： An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M
摘要翻译：一种电子计算电路，用于实现一种将比特长度N减小到比特长度M的两个操作数的比特宽度的方法，因此，M

4. 发明申请

US20070011220A1 Electronic circuit for implementing a permutation operation 失效
标题翻译：用于实现置换操作的电子电路
公开(公告)号：US20070011220A1
公开(公告)日：2007-01-11
申请号：US11390791
申请日：2006-03-28
申请人： Jens Leenstra , Nicolas Maeding , Amaury Mevergnies , Hans-Werner Tast
发明人： Jens Leenstra , Nicolas Maeding , Amaury Mevergnies , Hans-Werner Tast
IPC分类号： G06F17/15
CPC分类号： G06F7/766
摘要： A crossbar (20) circuit with multiplexer (22A, 22B) circuits implemented in a polygonal form on a chip. The crossbar can be used for implementing a permutation of input bits (24A, 24B) controlled by a bit vector (25). Horizontal and vertical wiring lengths in the crossbar (20) are reduced by stacking the operand latches (24A, 24B, 25) and horizontal or vertical multiplexers (22A, 22B). This implementation decreases the latency of the crossbar and avoids latches to store intermediated results, thus reducing area and power consumption.
摘要翻译：具有以多边形形式在芯片上实现的多路复用器（22A，22B）电路的交叉开关（20）电路。交叉开关可用于实现由位向量（25）控制的输入位（24A，24B）的置换。通过堆叠操作数锁存器（24A，24B，25）和水平或垂直多路复用器（22A，22B）来减小横杆（20）中的水平和垂直布线长度。该实现降低了交叉开关的延迟，并避免了锁存器来存储中间结果，从而减少了面积和功耗。

5. 发明授权

US08046566B2 Method to reduce power consumption of a register file with multi SMT support 失效
标题翻译：减少具有多个SMT支持的寄存器文件功耗的方法
公开(公告)号：US08046566B2
公开(公告)日：2011-10-25
申请号：US12120958
申请日：2008-05-15
申请人： Christopher M. Abernathy , Jens Leenstra , Nicolas Maeding , Dung Quoc Nguyen
发明人： Christopher M. Abernathy , Jens Leenstra , Nicolas Maeding , Dung Quoc Nguyen
IPC分类号： G06F9/50 , G06F1/32
CPC分类号： G06F1/3203
摘要： A method for reducing the power consumption of a register file of a microprocessor supporting simultaneous multithreading (SMT) is disclosed. Mapping logic and associated table entries monitor a total number of processing threads currently executing in the processor and signal control logic to disable specific register file entries not required for currently executing or pending instruction threads or register file entries not meeting a minimum access threshold using a least recently used algorithm (LRU). The register file utilization is controlled such that a register file address range selected for deactivation is not assigned for pending or future instruction threads. One or more power saving techniques are then applied to disabled register files to reduce overall power dissipation in the system.
摘要翻译：公开了一种降低支持同时多线程（SMT）的微处理器的寄存器堆的功耗的方法。映射逻辑和关联的表条目监视当前在处理器和信号控制逻辑中执行的处理线程的总数，以禁用当前执行或挂起的指令线程所不需要的特定寄存器文件条目或使用最少的不满足最小访问阈值的寄存器文件条目最近使用的算法（LRU）。控制寄存器文件利用率，使得为未停用或将来的指令线程未分配选择用于去激活的寄存器文件地址范围。然后将一种或多种省电技术应用于禁用的寄存器文件，以减少系统中的总体功耗。

6. 发明申请

US20090292892A1 Method to Reduce Power Consumption of a Register File with Multi SMT Support 失效
标题翻译：降低多SMT支持寄存器文件功耗的方法
公开(公告)号：US20090292892A1
公开(公告)日：2009-11-26
申请号：US12120958
申请日：2008-05-15
申请人： Christopher M. Abernathy , Jens Leenstra , Nicolas Maeding , Dung Quoc Nguyen
发明人： Christopher M. Abernathy , Jens Leenstra , Nicolas Maeding , Dung Quoc Nguyen
IPC分类号： G06F1/32 , G06F12/02
CPC分类号： G06F1/3203
摘要： A method for reducing the power consumption of a register file of a microprocessor supporting simultaneous multithreading (SMT) is disclosed. Mapping logic and associated table entries monitor a total number of processing threads currently executing in the processor and signal control logic to disable specific register file entries not required for currently executing or pending instruction threads or register file entries not meeting a minimum access threshold using a least recently used algorithm (LRU). The register file utilization is controlled such that a register file address range selected for deactivation is not assigned for pending or future instruction threads. One or more power saving techniques are then applied to disabled register files to reduce overall power dissipation in the system.
摘要翻译：公开了一种降低支持同时多线程（SMT）的微处理器的寄存器堆的功耗的方法。映射逻辑和关联的表条目监视当前在处理器和信号控制逻辑中执行的处理线程的总数，以禁用当前执行或挂起的指令线程所不需要的特定寄存器文件条目或使用最少的不满足最小访问阈值的寄存器文件条目最近使用的算法（LRU）。控制寄存器文件利用率，使得为未停用或将来的指令线程未分配选择用于去激活的寄存器文件地址范围。然后将一种或多种省电技术应用于禁用的寄存器文件，以减少系统中的总体功耗。

7. 发明申请

US20070180016A1 METHOD OF OPERAND WIDTH REDUCTION TO ENABLE USAGE OF NARROWER SATURATION ADDER 失效
标题翻译：操作方法可以减少使用NARROWER饱和添加剂的宽度
公开(公告)号：US20070180016A1
公开(公告)日：2007-08-02
申请号：US11560165
申请日：2006-11-15
申请人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Kerstin Schelm
发明人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Kerstin Schelm
IPC分类号： G06F7/50
CPC分类号： G06F7/49921
摘要： An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M
摘要翻译：一种电子计算电路，用于实现一种将比特长度N减小到比特长度M的两个操作数的比特宽度的方法，因此，M

8. 发明授权

US07890901B2 Method and system for verifying the equivalence of digital circuits 有权
标题翻译：用于验证数字电路等效性的方法和系统
公开(公告)号：US07890901B2
公开(公告)日：2011-02-15
申请号：US11684899
申请日：2007-03-12
申请人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Hari Mony
发明人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Hari Mony
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/504
摘要： The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding special wrappers (Wrapper A, Wrapper B), and used to equalize the timing of pairs of selected input signals and selected output signals of the logic designs. The wrappers drive certain signals of the designs that are not relevant for actual comparison, such signals including clock signals, clock control signals, scan-path signals, scan-path control signals, and reset signals. In a preferred embodiment, HDL descriptions of logic designs are analyzed. Based on this analysis, the wrappers are implemented as changes to the HDL descriptions. In another embodiment, RTL and/or gate-level netlists are analyzed and modified.
摘要翻译：比较了数字电路的等效设计的自动验证，其中以不同的硬件描述语言（HDL）实现的逻辑设计和不同的设计方法进行了比较。通过添加特殊包装器（Wrapper A，Wrapper B）来修改设计（代码A，代码B），并用于均衡所选输入信号对的时序和逻辑设计的选定输出信号。封装器驱动与实际比较无关的设计的某些信号，包括时钟信号，时钟控制信号，扫描路径信号，扫描路径控制信号和复位信号等信号。在优选实施例中，分析逻辑设计的HDL描述。基于这种分析，包装器被实现为对HDL描述的改变。在另一个实施例中，分析和修改RTL和/或门级网表。

9. 发明授权

US07783690B2 Electronic circuit for implementing a permutation operation 失效
标题翻译：用于实现置换操作的电子电路
公开(公告)号：US07783690B2
公开(公告)日：2010-08-24
申请号：US11390791
申请日：2006-03-28
申请人： Jens Leenstra , Nicolas Maeding , Amaury Neve de Mevergnies , Hans-Werner Tast
发明人： Jens Leenstra , Nicolas Maeding , Amaury Neve de Mevergnies , Hans-Werner Tast
IPC分类号： G06F15/00
CPC分类号： G06F7/766
摘要： A crossbar (20) circuit with multiplexer (22A, 22B) circuits implemented in a polygonal form on a chip. The crossbar can be used for implementing a permutation of input bits (24A, 24B) controlled by a bit vector (25). Horizontal and vertical wiring lengths in the crossbar (20) are reduced by stacking the operand latches (24A, 24B, 25) and horizontal or vertical multiplexers (22A, 22B). This implementation decreases the latency of the crossbar and avoids latches to store intermediated results, thus reducing area and power consumption.
摘要翻译：具有以多边形形式在芯片上实现的多路复用器（22A，22B）电路的交叉开关（20）电路。交叉开关可用于实现由位向量（25）控制的输入位（24A，24B）的置换。通过堆叠操作数锁存器（24A，24B，25）和水平或垂直多路复用器（22A，22B）来减小横杆（20）中的水平和垂直布线长度。该实现降低了交叉开关的延迟，并避免了锁存器来存储中间结果，从而减少了面积和功耗。

10. 发明申请

US20070226664A1 METHOD AND SYSTEM FOR VERIFYING THE EQUIVALENCE OF DIGITAL CIRCUITS 有权
标题翻译：用于验证数字电路等效性的方法和系统
公开(公告)号：US20070226664A1
公开(公告)日：2007-09-27
申请号：US11684899
申请日：2007-03-12
申请人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Hari Mony
发明人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding special wrappers (Wrapper A, Wrapper B), and used to equalize the timing of pairs of selected input signals and selected output signals of the logic designs. The wrappers drive certain signals of the designs that are not relevant for actual comparison, such signals including clock signals, clock control signals, scan-path signals, scan-path control signals, and reset signals. In a preferred embodiment, HDL descriptions of logic designs are analyzed. Based on this analysis, the wrappers are implemented as changes to the HDL descriptions. In another embodiment, RTL and/or gate-level netlists are analyzed and modified.
摘要翻译：比较了数字电路的等效设计的自动验证，其中以不同的硬件描述语言（HDL）实现的逻辑设计和不同的设计方法进行了比较。通过添加特殊包装器（Wrapper A，Wrapper B）来修改设计（代码A，代码B），并用于均衡所选输入信号对的时序和逻辑设计的选定输出信号。封装器驱动与实际比较无关的设计的某些信号，包括时钟信号，时钟控制信号，扫描路径信号，扫描路径控制信号和复位信号等信号。在优选实施例中，分析逻辑设计的HDL描述。基于这种分析，包装器被实现为对HDL描述的改变。在另一个实施例中，分析和修改RTL和/或门级网表。

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