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1. 发明授权

US09647976B2 Method and device for implementing end-to-end hardware message passing 有权
公开(公告)号：US09647976B2
公开(公告)日：2017-05-09
申请号：US14369963
申请日：2012-05-14
申请人： Cissy Yuan , Zhigang Zhu , Jian Wang , Xuehong Tian , Daibing Zeng , Wanting Tian , Fang Qiu
发明人： Cissy Yuan , Zhigang Zhu , Jian Wang , Xuehong Tian , Daibing Zeng , Wanting Tian , Fang Qiu
IPC分类号： G06F15/16 , G06F15/173 , H04L12/58 , G06F13/38 , H04L29/06
CPC分类号： H04L51/36 , G06F13/382 , H04L29/06 , H04L69/16 , H04L69/161
摘要： A method and device for implementing end-to-end Hardware Message Passing (HMP) are disclosed. The device includes: a message memory, a controller, a message input interface and a message output interface. The message memory is configured to temporarily store a message. The controller is configured to perform management on a message in the form of hardware, store a message obtained from the message input interface into the message memory, and read a message from the message memory and transmit the message to a message user via the message output interface. The message input interface is directly connected with a message creator and is configured to obtain a message created by the message creator under the control of the controller. The message output interface is directly connected to the message and is configured to provide a message to the message user under the control of the controller. The disclosure can improve the efficiency of message passing and reduce software management overhead.

2. 发明申请

US20150012714A1 Method and System for Multiple Processors to Share Memory 审中-公开
标题翻译：多处理器共享内存的方法和系统
公开(公告)号：US20150012714A1
公开(公告)日：2015-01-08
申请号：US14369926
申请日：2012-05-08
申请人： Cissy Yuan , Fang Qiu , Xuehong Tian , Wanting Tian , Daibing Zeng , Zhigang Zhu
发明人： Cissy Yuan , Fang Qiu , Xuehong Tian , Wanting Tian , Daibing Zeng , Zhigang Zhu
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0673 , G06F12/0831 , G06F13/1663 , G06F15/167 , G06F2003/0697
摘要： A method and system for multiple processors to share memory are disclosed. The method includes that: at least one local interconnection network is set, each of which is connected with at least two function modules; a local shared memory unit connected with the local interconnection network is set, and address space of each function module is mapped to the local shared memory unit; a first function module of the at least two function modules writes processed initial data into the local shared memory unit through the local interconnection network; and a second function module of the at least two function modules acquires data from the local shared memory unit via the local interconnection network. The technical solution of the disclosure can solve the drawbacks that a conventional system for multiple processors to globally share memory suffers a large transmission delay, high management overhead and the like.
摘要翻译：公开了一种用于共享存储器的多处理器的方法和系统。该方法包括：设置至少一个局部互连网络，每个互连网络与至少两个功能模块相连接; 设置与本地互连网络连接的本地共享存储器单元，并且将每个功能模块的地址空间映射到本地共享存储器单元; 所述至少两个功能模块的第一功能模块通过所述本地互连网络将经处理的初始数据写入所述本地共享存储器单元; 并且所述至少两个功能模块的第二功能模块经由所述本地互连网络从所述本地共享存储器单元获取数据。本公开的技术方案可以解决用于多处理器的常规系统全局共享存储器的缺点，其具有大的传输延迟，高管理开销等。

3. 发明授权

US09804985B2 Hardware abstract data structure, data processing method and system 有权
公开(公告)号：US09804985B2
公开(公告)日：2017-10-31
申请号：US14369903
申请日：2012-05-08
申请人： Cissy Yuan , Erkun Mao , Jian Wang , Xuehong Tian , Daibing Zeng , Wanting Tian , Qian Chen
发明人： Cissy Yuan , Erkun Mao , Jian Wang , Xuehong Tian , Daibing Zeng , Wanting Tian , Qian Chen
IPC分类号： G06F13/40 , G06F5/06 , G06F9/445 , G06F7/78
CPC分类号： G06F13/4004 , G06F5/06 , G06F7/78 , G06F9/44505
摘要： A Hardware Abstract Data Structure (HADS) includes a General Interface (GI), a Coherence Interface (CI), a Control and Configuration Logic (CCL), an Intelligence Logic (IL) and a Memory Pool (MP), wherein the GI is arranged to implement intercommunion between the HADS and a processor; the CI is arranged to implement coherence storage between multiple processors; the CCL is arranged to, in response to a command received by the GI, configure a hardware data structure for the MP; the IL is arranged to complete a large amount of simple and frequent data processing; and the MP is arranged to store data. Correspondingly, a method and data processing system are also disclosed. Through the disclosure, the HADS which is dynamically configurable, flexible, efficient, universal in interface and good in interconnectivity can be implemented to improve the data processing efficiency.

4. 发明申请

US20150032930A1 Hardware abstract data structure, data processing method and system 有权
标题翻译：硬件抽象数据结构，数据处理方法和系统
公开(公告)号：US20150032930A1
公开(公告)日：2015-01-29
申请号：US14369903
申请日：2012-05-08
申请人： Cissy Yuan , Erkun Mao , Jian Wang , Xuehong Tian , Daibing Zeng , Wanting Tian , Qian Chen
发明人： Cissy Yuan , Erkun Mao , Jian Wang , Xuehong Tian , Daibing Zeng , Wanting Tian , Qian Chen
IPC分类号： G06F13/40 , G06F9/445
CPC分类号： G06F13/4004 , G06F5/06 , G06F7/78 , G06F9/44505
摘要： A Hardware Abstract Data Structure (HADS) includes a General Interface (GI), a Coherence Interface (CI), a Control and Configuration Logic (CCL), an Intelligence Logic (IL) and a Memory Pool (MP), wherein the GI is arranged to implement intercommunion between the HADS and a processor; the CI is arranged to implement coherence storage between multiple processors; the CCL is arranged to, in response to a command received by the GI, configure a hardware data structure for the MP; the IL is arranged to complete a large amount of simple and frequent data processing; and the MP is arranged to store data. Correspondingly, a method and data processing system are also disclosed. Through the disclosure, the HADS which is dynamically configurable, flexible, efficient, universal in interface and good in interconnectivity can be implemented to improve the data processing efficiency.
摘要翻译：硬件抽象数据结构（HADS）包括通用接口（GI），连贯接口（CI），控制和配置逻辑（CCL），智能逻辑（IL）和存储器池（MP）），其中GI是安排实现HADS与处理器之间的互通; CI被设置为在多个处理器之间实现一致性存储; CCL被配置为响应于GI接收的命令，为MP配置硬件数据结构; 安排IL完成大量简单和频繁的数据处理; 并且MP被安排来存储数据。相应地，还公开了一种方法和数据处理系统。通过公开，可以实现动态配置，灵活，高效，通用通用和互连性好的HADS，以提高数据处理效率。

5. 发明申请

US20150309937A1 Intelligence cache and intelligence terminal 有权
标题翻译：智能缓存和智能终端
公开(公告)号：US20150309937A1
公开(公告)日：2015-10-29
申请号：US14375720
申请日：2012-06-29
申请人： Cissy Yuan , Erkun Mao , Qian Chen , Jian Wang , Xuehong Tian , Daibing Zeng , Wanting Tian
发明人： Cissy Yuan , Erkun Mao , Qian Chen , Jian Wang , Xuehong Tian , Daibing Zeng , Wanting Tian
IPC分类号： G06F12/08 , G06F17/30
CPC分类号： G06F12/0864 , G06F12/0831 , G06F12/0862 , G06F12/0893 , G06F17/30982 , G06F2212/1012 , G06F2212/601 , G06F2212/6032 , G06F2212/621
摘要： The disclosure discloses an intelligence cache and an intelligence terminal, wherein the intelligence cache comprises: a general interface, configured to receive configuration information and/or control information, and/or data information from a core a bus, and return target data; a software define and reconfiguration unit configured to define a memory as a required cache memory according to the configuration information; a control unit, configured to control writing and reading of the cache memory and monitor instructions and data streams in real time; a memory unit, composed of a number of memory modules and configured to cache data; the required cache memory is formed by memory modules according to the definition of the software define and reconfiguration unit; and an intelligence processing unit, configured to process input and output data and transfer, convert and operate on data among multiple structures defined in the control unit. The disclosure can realize an efficient memory system according to the operating status of software, the features of tasks to be executed and the features of data structures through the flexible organization and management by the control unit and the close cooperation of the intelligence processing unit.
摘要翻译：本公开公开了一种智能缓存和智能终端，其中所述智能缓存包括：通用接口，被配置为从总线接收配置信息和/或控制信息和/或数据信息，并返回目标数据; 软件定义和重新配置单元，被配置为根据配置信息将存储器定义为所需高速缓冲存储器; 控制单元，被配置为控制高速缓冲存储器的写入和读取并且实时监视指令和数据流; 存储器单元，由多个存储器模块组成并被配置为缓存数据; 所需的高速缓存由内存模块根据软件定义和重新配置单元的定义形成; 以及智能处理单元，被配置为处理输入和输出数据并在所述控制单元中定义的多个结构之间传送，转换和操作数据。本公开可以通过控制单元的灵活组织管理和智能处理单元的密切配合，根据软件的运行状态，要执行的任务的特点和数据结构的特点，实现高效的存储系统。

6. 发明授权

US09632940B2 Intelligence cache and intelligence terminal 有权
公开(公告)号：US09632940B2
公开(公告)日：2017-04-25
申请号：US14375720
申请日：2012-06-29
申请人： Cissy Yuan , Erkun Mao , Qian Chen , Jian Wang , Xuehong Tian , Daibing Zeng , Wanting Tian
发明人： Cissy Yuan , Erkun Mao , Qian Chen , Jian Wang , Xuehong Tian , Daibing Zeng , Wanting Tian
IPC分类号： G06F12/00 , G06F12/0864 , G06F12/0893 , G06F12/0862 , G06F12/0831 , G06F17/30
CPC分类号： G06F12/0864 , G06F12/0831 , G06F12/0862 , G06F12/0893 , G06F17/30982 , G06F2212/1012 , G06F2212/601 , G06F2212/6032 , G06F2212/621
摘要： The disclosure discloses an intelligence cache and an intelligence terminal, wherein the intelligence cache comprises: a general interface, configured to receive configuration information and/or control information, and/or data information from a core a bus, and return target data; a software define and reconfiguration unit configured to define a memory as a required cache memory according to the configuration information; a control unit, configured to control writing and reading of the cache memory and monitor instructions and data streams in real time; a memory unit, composed of a number of memory modules and configured to cache data; the required cache memory is formed by memory modules according to the definition of the software define and reconfiguration unit; and an intelligence processing unit, configured to process input and output data and transfer, convert and operate on data among multiple structures defined in the control unit. The disclosure can realize an efficient memory system according to the operating status of software, the features of tasks to be executed and the features of data structures through the flexible organization and management by the control unit and the close cooperation of the intelligence processing unit.

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