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1. 发明申请

US20130242985A1 MULTICAST BANDWIDTH MULTIPLICATION FOR A UNIFIED DISTRIBUTED SWITCH 有权
公开(公告)号：US20130242985A1
公开(公告)日：2013-09-19
申请号：US13420180
申请日：2012-03-14
申请人： Claude Basso , Todd A. Greenfield , Philip R. Hillier, III , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool , Bruce M. Walk
发明人： Claude Basso , Todd A. Greenfield , Philip R. Hillier, III , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool , Bruce M. Walk
IPC分类号： H04L12/56
CPC分类号： H04L45/16 , H04L49/201 , H04L49/351 , H04L49/70
摘要： The distributed switch may include a plurality of chips (i.e., sub-switches) on a switch module. These sub-switches may receive from a computing device connected to a Tx/Rx port a multicast data frame (e.g., an Ethernet frame) that designates a plurality of different destinations. Instead of simply using one egress connection interface to forward the copies of the data frame to each of the destinations sequentially, the sub-switch may use a plurality of a connection interfaces to transfer copies of the multicast data frame simultaneously. The port that receives the multicast data frame can borrow the connection interfaces (and associated hardware such as buffers) assigned to these other ports to transmit copies of the multicast data frame simultaneously.

2. 发明授权

US08897301B2 Multicast bandwidth multiplication for a unified distributed switch 有权
标题翻译：统一分布式交换机的组播带宽乘法
公开(公告)号：US08897301B2
公开(公告)日：2014-11-25
申请号：US13420180
申请日：2012-03-14
申请人： Claude Basso , Todd A. Greenfield , Philip R. Hillier, III , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool , Bruce M. Walk
发明人： Claude Basso , Todd A. Greenfield , Philip R. Hillier, III , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool , Bruce M. Walk
IPC分类号： H04L12/28 , H04L12/50 , H04L12/54 , H04J3/24 , H04J3/26 , G06F15/167
CPC分类号： H04L45/16 , H04L49/201 , H04L49/351 , H04L49/70
摘要： The distributed switch may include a plurality of chips (i.e., sub-switches) on a switch module. These sub-switches may receive from a computing device connected to a Tx/Rx port a multicast data frame (e.g., an Ethernet frame) that designates a plurality of different destinations. Instead of simply using one egress connection interface to forward the copies of the data frame to each of the destinations sequentially, the sub-switch may use a plurality of a connection interfaces to transfer copies of the multicast data frame simultaneously. The port that receives the multicast data frame can borrow the connection interfaces (and associated hardware such as buffers) assigned to these other ports to transmit copies of the multicast data frame simultaneously.
摘要翻译：分布式交换机可以包括交换机模块上的多个芯片（即子交换机）。这些子交换机可以从连接到Tx / Rx端口的计算设备接收指定多个不同目的地的多播数据帧（例如，以太网帧）。代替简单地使用一个出口连接接口将数据帧的副本顺序地转发到每个目的地，子交换机可以使用多个连接接口来同时传送多播数据帧的副本。接收组播数据帧的端口可以借用分配给这些其他端口的连接接口（以及相关的硬件，如缓冲区），同时传输组播数据帧的副本。

3. 发明申请

US20090271532A1 Early header CRC in data response packets with variable gap count 审中-公开
标题翻译：数据响应报文中的早期报头CRC可变间隙计数
公开(公告)号：US20090271532A1
公开(公告)日：2009-10-29
申请号：US12108744
申请日：2008-04-24
申请人： Brian D. Allison , Wayne M. Barrett , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool
发明人： Brian D. Allison , Wayne M. Barrett , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool
IPC分类号： G06F13/14
CPC分类号： G06F11/1004
摘要： A method is provided for processing a command issued by a processor over a bus. The method includes (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a header CRC; (3) validating the response packet including the header and the header CRC; (4) loading a timer to run until data required to complete the command is received or the timer expires; and (5) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.
摘要翻译：提供了一种用于处理由总线发出的处理器的命令的方法。该方法包括（1）将命令发送到远程节点以获得完成命令所需的数据; （2）从远程节点接收包括报头和报头CRC的响应分组; （3）验证包括报头和报头CRC的响应报文; （4）加载定时器运行，直到接收完成命令所需的数据或定时器到期; 和（5）在接收完成命令所需的数据之前，安排通过总线将数据返回给处理器。

4. 发明申请

US20090268736A1 Early header CRC in data response packets with variable gap count 审中-公开
标题翻译：数据响应报文中的早期报头CRC可变间隙计数
公开(公告)号：US20090268736A1
公开(公告)日：2009-10-29
申请号：US12108637
申请日：2008-04-24
申请人： Brian D. Allison , Wayne M. Barrett , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool
发明人： Brian D. Allison , Wayne M. Barrett , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool
IPC分类号： H04L12/56
CPC分类号： H04L1/0061 , H04L1/0072 , H04L2001/0094
摘要： A method is provided for processing commands issued by a processor over a bus. The method includes the steps of (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a header CRC; (3) validating the response packet based on the header CRC; and (4) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.
摘要翻译：提供了一种处理由总线发出的命令的方法。该方法包括以下步骤：（1）将命令发送到远程节点以获得对完成命令所需的数据的访问; （2）从远程节点接收包括报头和报头CRC的响应分组; （3）基于报头CRC验证响应分组; 和（4）在接收完成命令所需的数据之前，安排通过总线将数据返回到处理器。

5. 发明申请

US20090268727A1 Early header CRC in data response packets with variable gap count 审中-公开
标题翻译：数据响应报文中的早期报头CRC可变间隙计数
公开(公告)号：US20090268727A1
公开(公告)日：2009-10-29
申请号：US12108735
申请日：2008-04-24
申请人： Brian D. Allison , Wayne M. Barrett , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool
发明人： Brian D. Allison , Wayne M. Barrett , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool
IPC分类号： H04L12/56
CPC分类号： H04L69/22 , H04L69/324
摘要： A method is provided for processing a command issued by a processor over a bus. The method includes (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a variable gap; and (3) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.
摘要翻译：提供了一种用于处理由总线发出的处理器的命令的方法。该方法包括（1）将命令发送到远程节点以获得完成命令所需的数据; （2）从远程节点接收包括报头和可变间隙的响应分组; 和（3）在接收完成命令所需的数据之前，安排通过总线将数据返回到处理器。

6. 发明申请

US20110261815A1 Multicasting Using a Multitiered Distributed Virtual Bridge Hierarchy 有权
标题翻译：使用多层分布式虚拟网桥层次结构进行组播
公开(公告)号：US20110261815A1
公开(公告)日：2011-10-27
申请号：US12767481
申请日：2010-04-26
申请人： William J. Armstrong , Claude Basso , Josep Cors , Kyle A. Lucke , David A. Shedivy , Kenneth M. Valk , Bruce M. Walk
发明人： William J. Armstrong , Claude Basso , Josep Cors , Kyle A. Lucke , David A. Shedivy , Kenneth M. Valk , Bruce M. Walk
IPC分类号： H04L12/56
CPC分类号： H04L12/4625 , H04L45/16
摘要： Systems and methods to multicast data frames are provided. A particular apparatus includes a plurality of computing nodes and a distributed virtual bridge. The distributed virtual bridge includes a plurality of bridge elements coupled to the plurality of computing nodes. The plurality of bridge elements are configured to forward a copy of a multicast data frame to the plurality of computing nodes using group member information associated with addresses of the plurality of server computers. A controlling bridge coupled to the plurality of bridge elements is configured to communicate the group member information to the plurality of bridge elements.
摘要翻译：提供了组播数据帧的系统和方法。特定装置包括多个计算节点和分布式虚拟桥。分布式虚拟桥包括耦合到多个计算节点的多个桥元件。多个桥元件被配置为使用与多个服务器计算机的地址相关联的组成员信息将多播数据帧的副本转发到多个计算节点。耦合到所述多个桥接元件的控制桥被配置为将所述组成员信息传递到所述多个桥接元件。

7. 发明授权

US08379642B2 Multicasting using a multitiered distributed virtual bridge hierarchy 有权
公开(公告)号：US08379642B2
公开(公告)日：2013-02-19
申请号：US12767481
申请日：2010-04-26
申请人： William J. Armstrong , Claude Basso , Josep Cors , Kyle A. Lucke , David A. Shedivy , Kenneth M. Valk , Bruce M. Walk
发明人： William J. Armstrong , Claude Basso , Josep Cors , Kyle A. Lucke , David A. Shedivy , Kenneth M. Valk , Bruce M. Walk
IPC分类号： H04L12/28
CPC分类号： H04L12/4625 , H04L45/16
摘要： Systems and methods to multicast data frames are provided. A particular apparatus includes a plurality of computing nodes and a distributed virtual bridge. The distributed virtual bridge includes a plurality of bridge elements coupled to the plurality of computing nodes. The plurality of bridge elements are configured to forward a copy of a multicast data frame to the plurality of computing nodes using group member information associated with addresses of the plurality of server computers. A controlling bridge coupled to the plurality of bridge elements is configured to communicate the group member information to the plurality of bridge elements.

8. 发明授权

US08594090B2 Multicasting using a multitiered distributed virtual bridge hierarchy 有权
标题翻译：使用多层分布式虚拟网桥层次结构进行组播
公开(公告)号：US08594090B2
公开(公告)日：2013-11-26
申请号：US13485766
申请日：2012-05-31
申请人： William J. Armstrong , Claude Basso , Josep Cors , Kyle A. Lucke , David A. Shedivy , Kenneth M. Valk , Bruce M. Walk
发明人： William J. Armstrong , Claude Basso , Josep Cors , Kyle A. Lucke , David A. Shedivy , Kenneth M. Valk , Bruce M. Walk
IPC分类号： H04L12/28
CPC分类号： H04L12/4625 , H04L45/16
摘要： Systems and methods to multicast data frames are provided. A particular apparatus includes a plurality of computing nodes and a distributed virtual bridge. The distributed virtual bridge includes a plurality of bridge elements coupled to the plurality of computing nodes. The plurality of bridge elements are configured to forward a copy of a multicast data frame to the plurality of computing nodes using group member information associated with addresses of the plurality of server computers. A controlling bridge coupled to the plurality of bridge elements is configured to communicate the group member information to the plurality of bridge elements.
摘要翻译：提供了组播数据帧的系统和方法。特定装置包括多个计算节点和分布式虚拟桥。分布式虚拟桥包括耦合到多个计算节点的多个桥元件。多个桥元件被配置为使用与多个服务器计算机的地址相关联的组成员信息将多播数据帧的副本转发到多个计算节点。耦合到所述多个桥接元件的控制桥被配置为将所述组成员信息传递到所述多个桥接元件。

9. 发明申请

US20120236858A1 MULTICASTING USING A MULTITIERED DISTRIBUTED VIRTUAL BRIDGE HIERARCHY 有权
标题翻译：使用多媒体分布式虚拟桥梁层次分析
公开(公告)号：US20120236858A1
公开(公告)日：2012-09-20
申请号：US13485766
申请日：2012-05-31
申请人： William J. Armstrong , Claude Basso , Josep Cors , Kyle A. Lucke , David A. Shedivy , Kenneth M. Valk , Bruce M. Walk
发明人： William J. Armstrong , Claude Basso , Josep Cors , Kyle A. Lucke , David A. Shedivy , Kenneth M. Valk , Bruce M. Walk
IPC分类号： H04L12/56
CPC分类号： H04L12/4625 , H04L45/16
摘要： Systems and methods to multicast data frames are provided. A particular apparatus includes a plurality of computing nodes and a distributed virtual bridge. The distributed virtual bridge includes a plurality of bridge elements coupled to the plurality of computing nodes. The plurality of bridge elements are configured to forward a copy of a multicast data frame to the plurality of computing nodes using group member information associated with addresses of the plurality of server computers. A controlling bridge coupled to the plurality of bridge elements is configured to communicate the group member information to the plurality of bridge elements.
摘要翻译：提供了组播数据帧的系统和方法。特定装置包括多个计算节点和分布式虚拟桥。分布式虚拟桥包括耦合到多个计算节点的多个桥元件。多个桥元件被配置为使用与多个服务器计算机的地址相关联的组成员信息将多播数据帧的副本转发到多个计算节点。耦合到所述多个桥接元件的控制桥被配置为将所述组成员信息传递到所述多个桥接元件。

10. 发明申请

US20080301376A1 Method, Apparatus, and System Supporting Improved DMA Writes 审中-公开
标题翻译：方法，设备和系统支持改进的DMA写入
公开(公告)号：US20080301376A1
公开(公告)日：2008-12-04
申请号：US11756039
申请日：2007-05-31
申请人： Brian D. Allison , David A. Shedivy , Kenneth M. Valk , Brian T. Vanderpool
发明人： Brian D. Allison , David A. Shedivy , Kenneth M. Valk , Brian T. Vanderpool
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： A memory controller receives a stream of DMA write operations and enqueues them in a queue enforcing a First-In First-Out (FIFO) order. Prior to processing a particular DMA write operation, the memory controller acquires coherency ownership of a target memory block and stores the result in a low latency array. In response to acquiring coherency ownership, this low latency array is updated to a coherency state signifying coherency ownership by the memory controller. In a pipelined array access, both the low latency array and the second array are accessed and if the lower latency second array indicates the particular coherency state with no collision indication, the memory controller signals that the particular DMA write operation can be performed, where the signaling occurs prior to results being obtained from the higher latency first array at the normal end of the array access pipeline. In response to the signaling, the memory controller performs an update to the memory subsystem indicated by the particular DMA write operation.
摘要翻译：存储器控制器接收DMA写操作流并将其排入队列中，执行先进先出（FIFO）顺序。在处理特定DMA写入操作之前，存储器控制器获取目标存储器块的一致性所有权并将结果存储在低延迟数组中。响应于获取一致性所有权，该低延迟阵列被更新为表示存储器控制器的一致性所有权的一致性状态。在流水线阵列访问中，访问低延迟阵列和第二阵列，并且如果较低等待时间的第二阵列指示没有冲突指示的特定一致性状态，则存储器控制器指示可以执行特定的DMA写操作，其中信号发生在从阵列访问管道的正常端的较高等待时间第一阵列获得的结果之前。响应于信令，存储器控制器对由特定DMA写操作指示的存储器子系统进行更新。

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