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1. 发明授权

US07843316B1 Power-on reset apparatus, systems, and methods 有权
标题翻译：上电复位装置，系统和方法
公开(公告)号：US07843316B1
公开(公告)日：2010-11-30
申请号：US11842862
申请日：2007-08-21
申请人： Cong Khieu
发明人： Cong Khieu
IPC分类号： H04Q5/22
CPC分类号： G06F1/24
摘要： Apparatus, systems, and methods may include providing a power-on reset function to many types of receiving circuitry, including processors, memories, and radio frequency identification (RFID) tag processing circuitry. Thus, the power-on reset function may be realized by applying a supply voltage to a power-on reset circuit coupled to the processing circuit of an RFID tag. Additional activity may include sensing a first current substantially independent of the supply voltage, sensing a second current substantially dependent on the supply voltage, and indicating a power-on reset condition based on a comparison between the first current and the second current. Additional apparatus, systems, and methods are disclosed.
摘要翻译：装置，系统和方法可以包括向许多类型的接收电路提供上电复位功能，包括处理器，存储器和射频识别（RFID）标签处理电路。因此，可以通过将电源电压施加到耦合到RFID标签的处理电路的上电复位电路来实现上电复位功能。附加活动可以包括感测基本上独立于电源电压的第一电流，感测基本上取决于电源电压的第二电流，以及基于第一电流和第二电流之间的比较来指示上电复位条件。公开了附加装置，系统和方法。

2. 发明授权

US5304918A Reference circuit for high speed integrated circuits 失效
标题翻译：高速集成电路参考电路
公开(公告)号：US5304918A
公开(公告)日：1994-04-19
申请号：US823787
申请日：1992-01-22
申请人： Cong Khieu
发明人： Cong Khieu
IPC分类号： G11C11/407 , G05F1/567 , G05F3/30 , G11C16/06 , G11C17/00 , H03F1/30 , G05F3/16
CPC分类号： G05F1/567 , G05F3/30 , Y10S323/907
摘要： A reference circuit for supplying current to high speed logic elements in an integrated circuit supplies less current when circuit temperature decreases while a supply voltage remains constant. The reference circuit supplies less current when the supply voltage increases while circuit temperature remains constant. A resistance with a temperature coefficient, in some embodiments a negative temperature coefficient, is used to decrease current flow in a first leg of an output mirror when temperature decreases. A feedback circuit is used to decrease current flow in the first leg of the output current mirror when the feedback circuit senses an increase in supply voltage by sensing a voltage change on a common control node of the output current mirror. The reference circuit sees many applications including supplying current to logic gates, input/output buffers, and sense amplifiers.
摘要翻译：当电源电压保持恒定时，当电路温度降低时，用于向集成电路中的高速逻辑元件供电的参考电路提供较小的电流。当电路电压升高而电路温度保持不变时，参考电路会提供较少的电流。当温度降低时，具有温度系数的电阻（在一些实施例中为负温度系数）用于减小输出镜的第一支路中的电流。当反馈电路通过感测输出电流镜的公共控制节点上的电压变化来感测电源电压的增加时，反馈电路用于减小输出电流镜的第一支路中的电流流动。参考电路看到许多应用，包括向逻辑门，输入/输出缓冲器和读出放大器提供电流。

3. 发明授权

US08349676B2 Electrostatic discharge management apparatus, systems, and methods 有权
标题翻译：静电放电管理装置，系统和方法
公开(公告)号：US08349676B2
公开(公告)日：2013-01-08
申请号：US13214044
申请日：2011-08-19
申请人： Cong Khieu , Yanjun Ma , Jaideep Mavoori
发明人： Cong Khieu , Yanjun Ma , Jaideep Mavoori
IPC分类号： H01L21/337
CPC分类号： H01L27/0251
摘要： Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a snap-back voltage protection mechanism. Such devices may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.
摘要翻译：装置，系统和方法可以包括通过使用具有非对准栅极的半导体器件来管理静电放电事件以实现快速反向电压保护机制。这样的器件可以通过掺杂半导体衬底以形成阱中的第一导电区域形成，形成阱中的源极区域和漏极区域之一，在衬底上沉积多晶硅层以建立栅极区域与源极区域和漏极区域中的一个重叠，并且形成由衬底支撑的集成电路以耦合到源极区域和漏极区域中的一个，以在集成电路和漏极区域之间的节点处提供快速恢复电压操作源极或漏极区。公开了附加装置，系统和方法。

4. 发明授权

US06222777B1 Output circuit for alternating multiple bit line per column memory architecture 有权
标题翻译：每列存储器架构交替多位线路的输出电路
公开(公告)号：US06222777B1
公开(公告)日：2001-04-24
申请号：US09289460
申请日：1999-04-09
申请人： Cong Khieu
发明人： Cong Khieu
IPC分类号： G11C1604
CPC分类号： G11C7/18
摘要： A memory has memory cells arranged in rows and columns. The memory cells of each row are coupled to a word line that is separate from word lines connecting to the memory cells of other rows. Each column has mutually exclusive subsets of memory cells. The memory cells are coupled to bit lines. Each bit line is coupled to a selected mutually exclusive subset of memory cells. The memory cells of a selected row output a cell voltage on the coupled bit lines when the coupled word line is asserted. A multiplexor receives the cell voltages on the bit lines. The multiplexor is responsive to column select signals to select one of the columns as a selected column, and outputs a multiplexor voltage corresponding to the cell voltage of the memory cell of the selected row and the selected column.
摘要翻译：存储器具有以行和列排列的存储单元。每行的存储单元被耦合到与连接到其他行的存储器单元的字线分离的字线。每列具有互斥的存储单元子集。存储单元耦合到位线。每个位线耦合到选定的相互排斥的存储器单元子集。所选行的存储单元在耦合的字线被断言时在耦合的位线上输出单元电压。多路复用器接收位线上的单元电压。多路复用器响应于列选择信号以选择一列作为选定的列，并且输出与所选行和所选列的存储单元的单元电压相对应的多路复用器电压。

5. 发明授权

US08035486B1 Radio frequency identification device power-on reset management 有权
标题翻译：射频识别装置上电复位管理
公开(公告)号：US08035486B1
公开(公告)日：2011-10-11
申请号：US12965687
申请日：2010-12-10
申请人： Cong Khieu
发明人： Cong Khieu
IPC分类号： H04Q5/22
CPC分类号： G06F1/24
摘要： Apparatus, systems, and methods may include providing a power-on reset function to many types of receiving circuitry, including radio frequency identification (RFID) tag processing circuitry. Thus, the power-on reset function may be realized by applying a supply voltage to a power-on reset circuit coupled to RFID tag processing circuitry. Operations may include sensing a first current substantially independent of the supply voltage, sensing a second current substantially dependent on the supply voltage, and indicating a power-on reset condition based on a comparison between the first current and the second current. Additional apparatus, systems, and methods are disclosed.
摘要翻译：装置，系统和方法可以包括向许多类型的接收电路提供上电复位功能，包括射频识别（RFID）标签处理电路。因此，可以通过将电源电压施加到耦合到RFID标签处理电路的上电复位电路来实现上电复位功能。操作可以包括感测基本上独立于电源电压的第一电流，感测基本上取决于电源电压的第二电流，以及基于第一电流和第二电流之间的比较来指示上电复位条件。公开了附加装置，系统和方法。

6. 发明授权

US06493790B1 Translation-lookaside buffer with current tracking reference circuit 失效
标题翻译：具有电流跟踪参考电路的翻转后视缓冲器
公开(公告)号：US06493790B1
公开(公告)日：2002-12-10
申请号：US09016207
申请日：1998-01-30
申请人： Cong Khieu , Xin Liu , Der-ren Chu , Lan Lee
发明人： Cong Khieu , Xin Liu , Der-ren Chu , Lan Lee
IPC分类号： G06F1210
CPC分类号： G06F12/1027 , G11C15/00 , G11C15/04
摘要： A translation-lookaside buffer includes a content-addressable memory (CAM) cell to generate a CAM current signal with a first transistor configuration having a set of transistors of a predetermined size and connection. A reference current circuit generates a reference current signal with a second transistor configuration corresponding to the first transistor configuration, with the exception of the size and connection of selected transistors. A match sense amplifier selectively generates a match signal in response to the CAM current signal and the reference current signal.
摘要翻译：翻译后备缓冲器包括内容寻址存储器（CAM）单元，用于产生具有预定尺寸和连接的一组晶体管的第一晶体管配置的CAM电流信号。除了所选晶体管的尺寸和连接之外，参考电流电路产生具有对应于第一晶体管配置的第二晶体管配置的参考电流信号。匹配读出放大器响应于CAM电流信号和参考电流信号选择性地产生匹配信号。

7. 发明申请

US20110298051A1 Electrostatic Discharge Management Apparatus, Systems, and Methods 有权
标题翻译：静电放电管理装置，系统和方法
公开(公告)号：US20110298051A1
公开(公告)日：2011-12-08
申请号：US13214044
申请日：2011-08-19
申请人： Cong Khieu , Yanjun Ma , Jaideep Mavoori
发明人： Cong Khieu , Yanjun Ma , Jaideep Mavoori
IPC分类号： H01L27/06 , H01L29/778
CPC分类号： H01L27/0251
摘要： Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a snap-back voltage protection mechanism. Such devices may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.
摘要翻译：装置，系统和方法可以包括通过使用具有非对准栅极的半导体器件来管理静电放电事件以实现快速反向电压保护机制。这样的器件可以通过掺杂半导体衬底以形成阱中的第一导电区域形成，形成阱中的源极区域和漏极区域之一，在衬底上沉积多晶硅层以建立栅极区域与源极区域和漏极区域中的一个重叠，并且形成由衬底支撑的集成电路以耦合到源极区域和漏极区域中的一个，以在集成电路和漏极区域之间的节点处提供快速恢复电压操作源极或漏极区。公开了附加装置，系统和方法。

8. 发明授权

US08022498B1 Electrostatic discharge management apparatus, systems, and methods 有权
标题翻译：静电放电管理装置，系统和方法
公开(公告)号：US08022498B1
公开(公告)日：2011-09-20
申请号：US11837810
申请日：2007-08-13
申请人： Cong Khieu , Yanjun Ma , Jaideep Mavoori
发明人： Cong Khieu , Yanjun Ma , Jaideep Mavoori
IPC分类号： H01L29/00
CPC分类号： H01L27/0251
摘要： Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a snap-back voltage protection mechanism. Such devices may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.
摘要翻译：装置，系统和方法可以包括通过使用具有非对准栅极的半导体器件来管理静电放电事件以实现快速反向电压保护机制。这样的器件可以通过掺杂半导体衬底以形成阱中的第一导电区域形成，形成阱中的源极区域和漏极区域之一，在衬底上沉积多晶硅层以建立栅极区域与源极区域和漏极区域中的一个重叠，并且形成由衬底支撑的集成电路以耦合到源极区域和漏极区域中的一个，以在集成电路和漏极区域之间的节点处提供快速恢复电压操作源极或漏极区。公开了附加装置，系统和方法。

9. 发明授权

US07872566B1 Radio frequency identification device power-on reset management 有权
公开(公告)号：US07872566B1
公开(公告)日：2011-01-18
申请号：US11965359
申请日：2007-12-27
申请人： Cong Khieu
发明人： Cong Khieu
IPC分类号： H04Q5/22
CPC分类号： G06F1/24
摘要： Apparatus, systems, and methods may include providing a power-on reset function to many types of receiving circuitry, including radio frequency identification (RFID) tag processing circuitry. Thus, the power-on reset function may be realized by applying a supply voltage to a power-on reset circuit coupled to RFID tag processing circuitry. Operations may include sensing a first current substantially independent of the supply voltage, sensing a second current substantially dependent on the supply voltage, and indicating a power-on reset condition based on a comparison between the first current and the second current. Additional apparatus, systems, and methods are disclosed.

10. 发明授权

US6163192A Negative pulse edge triggered flip-flop 失效
标题翻译：负脉冲沿触发触发器
公开(公告)号：US6163192A
公开(公告)日：2000-12-19
申请号：US259148
申请日：1999-02-26
申请人： Lan Lee , Hiep P. Ngo , Cong Khieu
发明人： Lan Lee , Hiep P. Ngo , Cong Khieu
IPC分类号： H03K3/037 , H03K3/356
CPC分类号： H03K3/037 , H03K3/35606
摘要： A negative edge triggered flip-flop generates an output pulse in response to a negative edge of a clock signal. A first set of nodes receives data input signals, and a second set of nodes receives select input signals for selecting one data input signal as a selected data input signal. The clock node receives the clock signal which has a positive edge and a negative edge. A header circuit connects to the second set of nodes and to the clock node, and integrates the clock signal with the select input signals to generate at least one control signal. A pulse generator circuit connects to the first set of nodes, the header circuit and the output node. The pulse generator circuit generates an output pulse on the output node in response to a control signal and the selected data input signal.
摘要翻译：负边沿触发触发器响应于时钟信号的负沿产生输出脉冲。第一组节点接收数据输入信号，第二组节点接收用于选择一个数据输入信号的选择输入信号作为选择的数据输入信号。时钟节点接收具有正边沿和负边沿的时钟信号。标题电路连接到第二组节点和时钟节点，并且将时钟信号与选择输入信号进行积分以产生至少一个控制信号。脉冲发生器电路连接到第一组节点，标题电路和输出节点。脉冲发生器电路响应于控制信号和选择的数据输入信号在输出节点上产生输出脉冲。

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