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1. 发明授权

US10768847B2 Persistent memory module and method thereof 有权
公开(公告)号：US10768847B2
公开(公告)日：2020-09-08
申请号：US15644486
申请日：2017-07-07
申请人： DELL PRODUCTS, LP
发明人： John E. Jenne
IPC分类号： G06F3/06 , G06F1/20 , G06F1/30
摘要： A memory module, such as an NVDIMM receives access requests from a master device at a memory port requesting information from a volatile memory of the memory module. In response to receiving a save operation command at a command port, such as during a power failure, the memory module transfers the information stored at the volatile memory to a nonvolatile memory of the memory module based upon a programmable transfer rate.

2. 发明申请

US20200133380A1 Method and Apparatus to Distribute Current Indicator to Multiple End-Points 审中-公开
公开(公告)号：US20200133380A1
公开(公告)日：2020-04-30
申请号：US16175832
申请日：2018-10-31
申请人： DELL PRODUCTS, LP
发明人： John E. Jenne
IPC分类号： G06F1/32 , G06F1/18 , H02M3/07 , H02J1/10
摘要： An information handling system includes a PSU current level combiner, a current level indication splitter, and a load element. The PSU current level combiner receives a PSU current level indication from each of a plurality of PSUs, and provides a system current level indication that indicates a total amount of current supplied by the PSUs. Each PSU current level indication is a current signal and wherein a current level of each PSU current level indication is proportional to the amount of current supplied by the associated PSU. The system current level indication is a current signal. A current level of the system current level indication is proportional to the total amount of current. The system current level indication splitter receives the system current level indication, and provides copies of the system current level indication. The load element receives a copy of the system current level indication, and modifies a behavior of the first load element based on the copy of the system current level indication.

3. 发明申请

US20180246647A1 System and Method for Storing Modified Data to an NVDIMM During a Save Operation 审中-公开
公开(公告)号：US20180246647A1
公开(公告)日：2018-08-30
申请号：US15445179
申请日：2017-02-28
申请人： DELL PRODUCTS, LP
发明人： Vadhiraj Sankaranarayanan , John E. Jenne , Quy N. Hoang
IPC分类号： G06F3/06
CPC分类号： G06F3/065 , G06F3/0619 , G06F3/0685
摘要： A DIMM includes a DRAM device and a non-volatile memory device. The DIMM is configured to determine that first data stored on the DRAM device is modified data and that second data stored on the DRAM device is unmodified data, and perform a save data operation to transfer the data from the DRAM device to the non-volatile memory device, wherein the save data operation comprises transferring the first data and not transferring the second data.

4. 发明申请

US20160231802A1 Method and Apparatus for System Control of a Central Processing Unit (CPU) Maximum Power Detector 有权
标题翻译：中央处理器（CPU）最大功率检测器的系统控制方法和装置
公开(公告)号：US20160231802A1
公开(公告)日：2016-08-11
申请号：US14619727
申请日：2015-02-11
申请人： Dell Products, LP
发明人： John E. Jenne , Shawn J. Dube , Sandor Farkas
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3243 , G06F1/263 , G06F1/30 , G06F1/3206 , G06F1/3212
摘要： A method and apparatus for system control of a central processing unit (CPU) maximum power detector are provided. in accordance with at least one embodiment, a decision is made as to whether a response of a maximum power detector of the CPU is to be altered. When the response is to be altered, a modified input level is provided to the maximum power detector to alter the response. As an example, the modified input level can prevent the maximum power detector from triggering a power throttling function. When the response is not to be altered, an existing input level for the maximum power detector is maintained. In accordance with at least one embodiment, an apparatus or information handling system can comprise a voltage regulator (VR), a current sensor, a CPU comprising a maximum power detector, and a digital to analog converter (DAC).
摘要翻译：提供了一种用于中央处理单元（CPU）最大功率检测器的系统控制的方法和装置。根据至少一个实施例，做出关于CPU的最大功率检测器的响应是否被改变的决定。当响应被改变时，修改的输入电平被提供给最大功率检测器以改变响应。作为示例，修改的输入电平可以防止最大功率检测器触发功率节流功能。当不改变响应时，维持最大功率检测器的现有输入电平。根据至少一个实施例，装置或信息处理系统可以包括电压调节器（VR），电流传感器，包括最大功率检测器的CPU和数模转换器（DAC）。

5. 发明授权

US10852808B2 Method and apparatus to distribute current indicator to multiple end-points 有权
公开(公告)号：US10852808B2
公开(公告)日：2020-12-01
申请号：US16175832
申请日：2018-10-31
申请人： DELL PRODUCTS, LP
发明人： John E. Jenne
IPC分类号： G06F1/18 , G06F1/32 , H02J1/10 , G06F1/3234 , H02M3/07
摘要： An information handling system includes a PSU current level combiner, a current level indication splitter, and a load element. The PSU current level combiner receives a PSU current level indication from each of a plurality of PSUs, and provides a system current level indication that indicates a total amount of current supplied by the PSUs. Each PSU current level indication is a current signal and wherein a current level of each PSU current level indication is proportional to the amount of current supplied by the associated PSU. The system current level indication is a current signal. A current level of the system current level indication is proportional to the total amount of current. The system current level indication splitter receives the system current level indication, and provides copies of the system current level indication. The load element receives a copy of the system current level indication, and modifies a behavior of the first load element based on the copy of the system current level indication.

6. 发明授权

US10459733B2 Power budgeting in an information handling system 有权
公开(公告)号：US10459733B2
公开(公告)日：2019-10-29
申请号：US15880058
申请日：2018-01-25
申请人： DELL PRODUCTS, LP
发明人： John E. Jenne , Kyle E. Cross
IPC分类号： G06F9/44 , G06F1/32 , G06F9/4401 , G06F1/3206
摘要： A halt event separates a boot up operation from a run time operation. A controller grants a request from a baseboard management controller for an electrical power associated with a boot-up operation. As the baseboard management controller completes the boot-up operation (such as a power on self-test), the baseboard management controller predicts the electrical power that is required for a run time operation (e.g., executing an operating system). The baseboard management controller is then required or forced to submit a subsequent request for the additional electrical power that is required for the run time operation. The controller compares the electrical power predicted for the run time operation to a power availability from a power supply (such as a safe or maximum operating condition). If the power supply can provide the electrical power predicted to be required during the run time operation, then the controller may permit or authorize a transition from the boot up operation to the run time operation. However, if the power supply cannot provide the electrical power predicted to be required during the run time operation, then the controller denies the run time operation.

7. 发明申请

US20180246643A1 System and Method to Perform Runtime Saves on Dual Data Rate NVDIMMs 审中-公开
公开(公告)号：US20180246643A1
公开(公告)日：2018-08-30
申请号：US15445236
申请日：2017-02-28
申请人： DELL PRODUCTS, LP
发明人： John E. Jenne , Vadhiraj Sankaranarayanan , Andrew Butcher
IPC分类号： G06F3/06 , G11C11/4096 , G11C11/4093
摘要： A DIMM includes a DRAM device and a non-volatile memory device. The DIMM is configured in a first mode to receive a save signal from a memory controller via a save pin of the DIMM and to perform a first save operation to transfer data from the DRAM device to the non-volatile memory device in response to receiving the save signal. The DIMM is further configured in a second mode to receive a save command from the memory controller via a command bus of the DIMM and to perform a second save operation to transfer the data from the DRAM device to the non-volatile memory device in response to receiving the save command.

8. 发明申请

US20160018875A1 Dynamic System Management Communication Path Selection 有权
标题翻译：动态系统管理通信路径选择
公开(公告)号：US20160018875A1
公开(公告)日：2016-01-21
申请号：US14867949
申请日：2015-09-28
申请人： Dell Products, LP
发明人： John E. Jenne , Vijay Nijhawan
IPC分类号： G06F1/32 , G06F13/16 , G06F13/42 , G06F13/40
CPC分类号： G06F1/3243 , G06F1/32 , G06F1/3206 , G06F13/1652 , G06F13/1678 , G06F13/4022 , G06F13/4282 , Y02D10/14 , Y02D10/151
摘要： An information handling system includes a processor, a controller hub, a shared higher bandwidth path coupling the processor to the controller hub, and an exclusive lower bandwidth path coupling the processor to the controller hub. The processor communicates system management information over the bandwidth path in response to a first set of criteria and communicates the information over the lower bandwidth path in response to the second set of criteria.
摘要翻译：信息处理系统包括处理器，控制器集线器，将处理器耦合到控制器集线器的共享更高带宽路径以及将处理器耦合到控制器集线器的专用低带宽路径。处理器响应于第一组标准通过带宽路径传送系统管理信息，并响应于第二组标准在较低带宽路径上传送信息。

9. 发明授权

US09146599B2 Dynamic system management communication path selection 有权
标题翻译：动态系统管理通信路径选择
公开(公告)号：US09146599B2
公开(公告)日：2015-09-29
申请号：US13898170
申请日：2013-05-20
申请人： Dell Products, LP
发明人： John E. Jenne , Vijay Nijhawan
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/32 , G06F1/3206 , G06F13/1652 , G06F13/1678 , G06F13/4022 , G06F13/4282 , Y02D10/14 , Y02D10/151
摘要： An information handling system includes a processor, a controller hub, a shared higher bandwidth path coupling the processor to the controller hub, and an exclusive lower bandwidth path coupling the processor to the controller hub. The processor communicates system management information over the bandwidth path in response to a first set of criteria and communicates the information over the lower bandwidth path in response to the second set of criteria.
摘要翻译：信息处理系统包括处理器，控制器集线器，将处理器耦合到控制器集线器的共享更高带宽路径以及将处理器耦合到控制器集线器的专用低带宽路径。处理器响应于第一组标准通过带宽路径传送系统管理信息，并响应于第二组标准在较低带宽路径上传送信息。

10. 发明申请

US20140380069A1 Date Adjusted Power Budgeting for an Information Handling System 有权
标题翻译：信息处理系统的日期调整功率预算
公开(公告)号：US20140380069A1
公开(公告)日：2014-12-25
申请号：US13924988
申请日：2013-06-24
申请人： Dell Products, LP
发明人： Stuart Allen Berke , John E. Jenne
IPC分类号： G06F1/32
CPC分类号： G06F1/32
摘要： An information handling system determines a system configuration including a hardware module, and determines an adjusted power budget for the hardware module. The adjusted power budget is based on a calculation including a difference between a date code read from the hardware module and a baseline date, a baseline power budget, a power reduction period and a power reduction interval. The calculation may optionally include a risk factor. In alternate embodiments, an adjusted power budget for a hardware module may be calculated by an order processing system for information handling systems, or by a planning tool for a data center which contains information handling systems.
摘要翻译：信息处理系统确定包括硬件模块的系统配置，并且确定用于硬件模块的经调整的功率预算。经调整的功率预算基于包括从硬件模块读取的日期代码与基线日期，基准功率预算，功率降低周期和功率降低间隔之间的差异的计算。计算可以可选地包括风险因素。在替代实施例中，用于硬件模块的经调整的功率预算可以由信息处理系统的订单处理系统或包含信息处理系统的数据中心的规划工具来计算。

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