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1. 发明申请

US20140335669A1 EMBEDDED NON-VOLATILE MEMORY 有权
公开(公告)号：US20140335669A1
公开(公告)日：2014-11-13
申请号：US14306801
申请日：2014-06-17
申请人： Daniel R. Shepard , Mac D. Apodaca , Thomas Michael Trent , James Juen Hsu
发明人： Daniel R. Shepard , Mac D. Apodaca , Thomas Michael Trent , James Juen Hsu
IPC分类号： H01L27/24 , H01L45/00 , H01L21/8238
CPC分类号： H01L27/2463 , H01L21/8238 , H01L27/04 , H01L27/1021 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

2. 发明授权

US08325556B2 Sequencing decoder circuit 有权
标题翻译：排序解码电路
公开(公告)号：US08325556B2
公开(公告)日：2012-12-04
申请号：US12575055
申请日：2009-10-07
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits includes first and second decoder stages. The first decoder stage selects one or more first rows by decoding a first subset of the address bits, and the second decoder stage selects one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows.
摘要翻译：可操作地耦合到存储器阵列的存储器阵列解码器，该存储器阵列包括一系列行并作为输入接收多个地址位，包括第一和第二解码器级。第一解码器级通过解码地址位的第一子集来选择一个或多个第一行，并且第二解码器级基于序列内的与一个或多个第三行不同的一个或多个第三行中的位置来选择一个或多个第二行，更多第二排。

3. 发明申请

US20110019455A1 LOW COST HIGH DENSITY RECTIFIER MATRIX MEMORY 有权
标题翻译：低成本高密度整流器矩阵存储器
公开(公告)号：US20110019455A1
公开(公告)日：2011-01-27
申请号：US12898205
申请日：2010-10-05
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G06K5/04 , G11C5/025 , G11C7/00 , G11C16/04 , G11C29/006 , G11C29/02 , G11C29/025 , G11C2029/5006 , H01L21/84 , H01L22/32 , H01L27/10 , H01L27/105 , H01L27/1052 , H01L27/12 , H01L2924/0002 , H01L2924/00
摘要： A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.
摘要翻译：三维地制造高密度存储器件。为了使故障点保持低电平，地址解码电路被包括在每个层内，使得除了功率和数据线之外，只有地址信号线需要在层之间互连。

4. 发明申请

US20100232200A1 VERTICAL SWITCH THREE-DIMENSIONAL MEMORY ARRAY 有权
标题翻译：垂直开关三维存储阵列
公开(公告)号：US20100232200A1
公开(公告)日：2010-09-16
申请号：US12720843
申请日：2010-03-10
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： G11C5/02 , H01L21/336 , G11C5/06
CPC分类号： G11C8/10 , G11C13/0002 , G11C13/0004 , G11C13/0023 , G11C17/12 , G11C17/16 , G11C17/18 , G11C2213/71 , H01L27/1021 , H01L27/1027 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L27/11517 , H01L27/2445 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L29/7827 , H01L29/87 , H01L45/04 , H01L45/06 , H01L45/124 , H01L45/144
摘要： A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. In some embodiments, each switch has at least three terminals and a cross-sectional area less than 6F2.
摘要翻译：存储器件包括衬底，并且在其上设置有垂直存储器开关阵列。在一些实施例中，每个开关具有至少三个端子和小于6F2的横截面面积。

5. 发明申请

US20090225579A1 LOW COST, HIGH-DENSITY RECTIFIER MATRIX MEMORY 有权
标题翻译：低成本，高密度整流器矩阵存储器
公开(公告)号：US20090225579A1
公开(公告)日：2009-09-10
申请号：US12265456
申请日：2008-11-05
申请人： Daniel R. Shepard , Thomas A. Langdo , Arthur J. Pitera
发明人： Daniel R. Shepard , Thomas A. Langdo , Arthur J. Pitera
IPC分类号： G11C5/02 , G11C8/10 , G11C7/00
CPC分类号： G11C5/02 , G11C5/06 , G11C13/00 , G11C13/0004 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/72 , H01L27/105
摘要： A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.
摘要翻译：高密度存储器件是三维地制造的。为了使故障点保持低电平，地址解码电路被包括在每个层内，使得除了功率和数据线之外，只有地址信号线需要在层之间互连。

6. 发明授权

US5889694A Dual-addressed rectifier storage device 失效
标题翻译：双路整流存储设备
公开(公告)号：US5889694A
公开(公告)日：1999-03-30
申请号：US863156
申请日：1997-05-27
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： G11C8/04 , G11C17/06 , H01L27/102 , H01L27/112
CPC分类号： G11C8/04 , G11C17/06 , G11C17/10 , H01L27/1021 , H01L27/112
摘要： A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed Rectifier Storage (DRS) Array very scaleable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.
摘要翻译：提供了只读数据存储和检索装置，其没有移动部件并且需要非常低的功率。可以顺序完成寻址，其中地址自动增加或可以随机完成。通过使用在两个坐标方向上寻址的高度对称的二极管矩阵来实现高密度存储; 其对称性使得双寻址整流器存储（DRS）阵列非常可扩展，特别是当作为集成电路时。为了获得更大的存储灵活性，可将多个数字整流器存储阵列并入设备中，其中一个或多个可以被制造为可移除和可互换的。

7. 发明申请

US20150155336A1 SOLID STATE DEVICES HAVING FINE PITCH STRUCTURES 有权
标题翻译：具有细微结构的固体装置
公开(公告)号：US20150155336A1
公开(公告)日：2015-06-04
申请号：US14616128
申请日：2015-02-06
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2463 , H01L21/0337 , H01L21/311 , H01L21/31144 , H01L27/1021 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.
摘要翻译：在各种实施例中，用于形成存储器阵列的方法包括形成多个硬掩模材料的行和列，使用硬掩模材料行和硬掩模列的组合掩蔽特性来蚀刻绝缘材料的一个或多个层中的孔材料，并在孔中形成记忆单元。孔的角可以是圆形的。

8. 发明申请

US20140329369A1 PINCHED CENTER RESISTIVE CHANGE MEMORY CELL 有权
标题翻译：夹紧中心电阻变化记忆体
公开(公告)号：US20140329369A1
公开(公告)日：2014-11-06
申请号：US14283714
申请日：2014-05-21
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： H01L45/00
CPC分类号： H01L45/1683 , H01L21/28273 , H01L27/2409 , H01L29/788 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1608
摘要： The present invention is a method for forming a vertically oriented element having a narrower area near its center away from either end. The present invention will find applicability in other memory cell structures. The element will have a narrow portion towards its center such that current density will be higher away from the ends of the element. In this way, the heating will occur away from the ends of the storage element. Heating in a phase-change or resistive change element leads to end of life conditions, including the condition whereby contaminants from the end point contacts are enabled to migrate away from the end point and into the storage element thereby contaminating the storage element material and reducing its ability to be programmed, erased and/or read back. By keeping the greatest heating towards the center of the element where it is surrounded by more of the same material and away from the ends of the element where end point contact material can be heated and potentially activated, the lifetime of the element will be increased.
摘要翻译：本发明是一种用于形成垂直定向元件的方法，该元件具有在远离任一端的中心附近具有较窄区域的方法。本发明将发现其它存储单元结构的适用性。元件将具有朝向其中心的窄部分，使得电流密度将远离元件的端部。以这种方式，加热将远离存储元件的端部。相变或电阻变化元件中的加热导致寿命终止状态，包括使来自端点接触的污染物能够远离端点迁移到存储元件中从而污染存储元件材料并降低其的条件编程，擦除和/或回读的能力。通过将最大的加热保持在元件的中心，在其中被更多的相同材料包围并远离元件的端部，其中端点接触材料可以被加热并潜在地被激活，元件的寿命将增加。

9. 发明授权

US08773881B2 Vertical switch three-dimensional memory array 有权
标题翻译：垂直开关三维记忆阵列
公开(公告)号：US08773881B2
公开(公告)日：2014-07-08
申请号：US12720843
申请日：2010-03-10
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： G11C5/02
CPC分类号： G11C8/10 , G11C13/0002 , G11C13/0004 , G11C13/0023 , G11C17/12 , G11C17/16 , G11C17/18 , G11C2213/71 , H01L27/1021 , H01L27/1027 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L27/11517 , H01L27/2445 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L29/7827 , H01L29/87 , H01L45/04 , H01L45/06 , H01L45/124 , H01L45/144
摘要： Methods of forming memory devices include providing a substrate, forming source, channel, and drain layers over the substrate, and patterning the source, channel, and drain layers into an array of memory switches each having a cross-sectional area less than 6 F2. The channel layer has a doping type different from a doping type of the source layer, and the drain layer has a doping type different from a doping type of the channel layer.
摘要翻译：形成存储器件的方法包括在衬底上提供衬底，形成源极，沟道和漏极层，以及将源极，沟道和漏极层图案化成具有小于6F2的横截面积的存储器开关阵列。沟道层具有与源极层的掺杂型不同的掺杂型，漏极层具有与掺杂型沟道层不同的掺杂型。

10. 发明授权

US08358526B2 Diagonal connection storage array 有权
标题翻译：对角线连接存储阵列
公开(公告)号：US08358526B2
公开(公告)日：2013-01-22
申请号：US12395071
申请日：2009-02-27
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C5/14
摘要： In one aspect, an electronic memory array includes overlapping, generally parallel sets of conductors, and includes storage elements near each point of overlap. One set of conductors has a non-negligible resistance. An address path for each storage element traverses a portion of one each of the first and second sets of conductors and a selectable resistance element. All storage element address paths have substantially equivalent voltage drops across the corresponding storage elements.
摘要翻译：在一个方面，电子存储器阵列包括重叠的，大致平行的导体组，并且包括在每个重叠点附近的存储元件。一组导体具有不可忽视的阻力。每个存储元件的地址路径遍及第一组和第二组导体中的每一个的一部分以及可选择的电阻元件。所有存储元件地址路径在对应的存储元件上具有基本相等的电压降。

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