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1. 发明申请

US20110185160A1 MULTI-CORE PROCESSOR WITH EXTERNAL INSTRUCTION EXECUTION RATE HEARTBEAT 有权
标题翻译：具有外部指令执行速率心脏的多核心处理器
公开(公告)号：US20110185160A1
公开(公告)日：2011-07-28
申请号：US12964949
申请日：2010-12-10
申请人： Darius D. Gaskins , Jason Chen , Rodney E. Hooker
发明人： Darius D. Gaskins , Jason Chen , Rodney E. Hooker
IPC分类号： G06F9/30 , G06F1/14 , G06F13/28
CPC分类号： G06F11/364 , G06F11/3652 , G06F11/3656
摘要： A method for debugging a multi-core microprocessor includes causing the microprocessor to perform an actual execution of instructions and obtaining from the microprocessor heartbeat information that specifies an actual execution sequence of the instructions by the plurality of cores relative to one another, commanding a corresponding plurality of instances of a software functional model of the cores to execute the instructions according to the actual execution sequence specified by the heartbeat information to generate simulated results of the execution of the instructions, and comparing the simulated results with actual results of the execution of the instructions to determine whether they match. Each core outputs an instruction execution indicator indicating the number of instructions executed by the core each core clock. A heartbeat generator generates a heartbeat indicator for each core on an external bus that indicates the number of instructions executed by each core during each external bus clock cycle.
摘要翻译：一种用于调试多核微处理器的方法包括使微处理器执行指令的实际执行，并从微处理器获得心跳信息，该信号指定多个核心相对于彼此的指令的实际执行顺序，命令相应的多个的核心的软件功能模型的实例，以根据由心跳信息指定的实际执行顺序来执行指令，以生成指令执行的模拟结果，并将模拟结果与指令执行的实际结果进行比较以确定它们是否匹配。每个核心输出指示执行指示符，指示核心每个核心时钟执行的指令数。心跳发生器为外部总线上的每个内核生成一个心跳指示符，指示每个外部总线时钟周期内由每个内核执行的指令数。

2. 发明授权

US08762779B2 Multi-core processor with external instruction execution rate heartbeat 有权
标题翻译：具有外部指令执行率心跳的多核处理器
公开(公告)号：US08762779B2
公开(公告)日：2014-06-24
申请号：US12964949
申请日：2010-12-10
申请人： Darius D. Gaskins , Jason Chen , Rodney E. Hooker
发明人： Darius D. Gaskins , Jason Chen , Rodney E. Hooker
IPC分类号： G06F11/00 , G06F11/36
CPC分类号： G06F11/364 , G06F11/3652 , G06F11/3656
摘要： A method for debugging a multi-core microprocessor includes causing the microprocessor to perform an actual execution of instructions and obtaining from the microprocessor heartbeat information that specifies an actual execution sequence of the instructions by the plurality of cores relative to one another, commanding a corresponding plurality of instances of a software functional model of the cores to execute the instructions according to the actual execution sequence specified by the heartbeat information to generate simulated results of the execution of the instructions, and comparing the simulated results with actual results of the execution of the instructions to determine whether they match. Each core outputs an instruction execution indicator indicating the number of instructions executed by the core each core clock. A heartbeat generator generates a heartbeat indicator for each core on an external bus that indicates the number of instructions executed by each core during each external bus clock cycle.
摘要翻译：一种用于调试多核微处理器的方法包括使微处理器执行指令的实际执行，并从微处理器获得心跳信息，该信号指定多个核心相对于彼此的指令的实际执行顺序，命令相应的多个的核心的软件功能模型的实例，以根据由心跳信息指定的实际执行顺序来执行指令，以生成指令执行的模拟结果，并将模拟结果与指令执行的实际结果进行比较以确定它们是否匹配。每个核心输出指示执行指示符，指示核心每个核心时钟执行的指令数。心跳发生器为外部总线上的每个内核生成一个心跳指示符，指示每个外部总线时钟周期内由每个内核执行的指令数。

3. 发明申请

US20110113196A1 AVOIDING MEMORY ACCESS LATENCY BY RETURNING HIT-MODIFIED WHEN HOLDING NON-MODIFIED DATA 有权
标题翻译：保存未经修改的数据时，通过恢复进行修改而避免内存访问延迟
公开(公告)号：US20110113196A1
公开(公告)日：2011-05-12
申请号：US12880958
申请日：2010-09-13
申请人： Rodney E. Hooker , Colin Eddy , Darius D. Gaskins , Albert J. Loper, JR.
发明人： Rodney E. Hooker , Colin Eddy , Darius D. Gaskins , Albert J. Loper, JR.
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A microprocessor is configured to communicate with other agents on a system bus and includes a cache memory and a bus interface unit coupled to the cache memory and to the system bus. The bus interface unit receives from another agent coupled to the system bus a transaction to read data from a memory address, determines whether the cache memory is holding the data at the memory address in an exclusive state (or a shared state in certain configurations), and asserts a hit-modified signal on the system bus and provides the data on the system bus to the other agent when the cache memory is holding the data at the memory address in an exclusive state. Thus, the delay of an access to the system memory by the other agent is avoided.
摘要翻译：微处理器被配置为与系统总线上的其他代理通信，并且包括高速缓存存储器和耦合到高速缓冲存储器和系统总线的总线接口单元。总线接口单元从耦合到系统总线的另一个代理接收从存储器地址读取数据的事务，确定高速缓冲存储器是否处于处于独占状态（或某些配置中的共享状态）的存储器地址处的数据，并且当高速缓冲存储器将数据保存在处于独占状态的存储器地址时，在系统总线上断言命中修正信号并将系统总线上的数据提供给另一个代理。因此，避免了其他代理对系统存储器的访问的延迟。

4. 发明授权

US08364906B2 Avoiding memory access latency by returning hit-modified when holding non-modified data 有权
标题翻译：在保存未修改的数据时，通过返回命中修改来避免内存访问延迟
公开(公告)号：US08364906B2
公开(公告)日：2013-01-29
申请号：US12880958
申请日：2010-09-13
申请人： Rodney E. Hooker , Colin Eddy , Darius D. Gaskins , Albert J. Loper, Jr.
发明人： Rodney E. Hooker , Colin Eddy , Darius D. Gaskins , Albert J. Loper, Jr.
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A microprocessor is configured to communicate with other agents on a system bus and includes a cache memory and a bus interface unit coupled to the cache memory and to the system bus. The bus interface unit receives from another agent coupled to the system bus a transaction to read data from a memory address, determines whether the cache memory is holding the data at the memory address in an exclusive state (or a shared state in certain configurations), and asserts a hit-modified signal on the system bus and provides the data on the system bus to the other agent when the cache memory is holding the data at the memory address in an exclusive state. Thus, the delay of an access to the system memory by the other agent is avoided.
摘要翻译：微处理器被配置为与系统总线上的其他代理通信，并且包括高速缓存存储器和耦合到高速缓冲存储器和系统总线的总线接口单元。总线接口单元从耦合到系统总线的另一个代理接收从存储器地址读取数据的事务，确定高速缓冲存储器是否处于处于独占状态（或某些配置中的共享状态）的存储器地址处的数据，并且当高速缓冲存储器将数据保存在处于独占状态的存储器地址时，在系统总线上断言命中修正信号并将系统总线上的数据提供给另一个代理。因此，避免了其他代理对系统存储器的访问的延迟。

5. 发明授权

US06681311B2 Translation lookaside buffer that caches memory type information 有权
标题翻译：缓存内存类型信息的翻译后备缓冲区
公开(公告)号：US06681311B2
公开(公告)日：2004-01-20
申请号：US09908909
申请日：2001-07-18
申请人： Darius D. Gaskins , G. Glenn Henry , Rodney E. Hooker
发明人： Darius D. Gaskins , G. Glenn Henry , Rodney E. Hooker
IPC分类号： G06F1200
CPC分类号： G06F12/1027
摘要： A translation lookaside buffer (TLB) that caches memory types of memory address ranges. A data unit includes a TLB which, in addition to caching page table entries including translated page base addresses of virtual page numbers as in a conventional TLB, also caches memory address range memory types provided by a memory type unit (MTU). In the case of a hit of a virtual address in the TLB, the TLB provides the memory type along with the page table entry, thereby avoiding the need for a serialized accessed to the MTU using the physical address output by the TLB. Logic which controls a processor bus access necessitated by the virtual address makes use of the memory type output by the TLB sooner than would be available from the MTU in conventional data units. If the MTU is updated, the TLB is flushed to insure consistency of memory type values.
摘要翻译：翻译后备缓冲区（TLB），缓存内存地址范围的内存类型。数据单元包括TLB，除了如在常规TLB中缓存包括虚拟页号的翻译页基地址的页表项之外，还缓存由存储器类型单元（MTU）提供的存储器地址范围存储器类型。在TLB中命中虚拟地址的情况下，TLB与页表项一起提供存储器类型，从而避免了使用TLB输出的物理地址对MTU的序列化访问的需要。控制由虚拟地址所必需的处理器总线访问的逻辑利用了比常规数据单元中MTU可用的存储器类型更早地由TLB输出的存储器类型。如果MTU更新，则刷新TLB以确保内存类型值的一致性。

6. 发明授权

US06675287B1 Method and apparatus for store forwarding using a response buffer data path in a write-allocate-configurable microprocessor 有权
标题翻译：用于在写入分配可配置的微处理器中使用响应缓冲器数据路径的存储转发的方法和装置
公开(公告)号：US06675287B1
公开(公告)日：2004-01-06
申请号：US09545026
申请日：2000-04-07
申请人： Darius D. Gaskins , G. Glenn Henry , Rodney E. Hooker
发明人： Darius D. Gaskins , G. Glenn Henry , Rodney E. Hooker
IPC分类号： G06F938
CPC分类号： G06F9/3834 , G06F9/3826
摘要： An apparatus for forwarding storehit data within a pipelined microprocessor is provided. The apparatus has a plurality of response buffers that receive data from a bus that couples a system memory to the microprocessor and multiplexing and forwarding logic. When a store instruction generates a miss of the microprocessor's instruction cache, the store results are written not only to store buffers for updating the cache, but also to one of the response buffers. The missing cache line implicated by the store miss is requested from the system memory, received into the response buffer, and merged with the store results. The cache is updated with the merged data. However, in addition, storehit conditions with the store results generated by load instructions coming down the pipeline are satisfied from the response buffer. The multiplexing and forwarding logic is capable of forwarding the store results from the response buffer to the pipeline both before and after the missing cache line is received.
摘要翻译：提供了一种用于在流水线微处理器内转发存储数据的装置。该装置具有多个响应缓冲器，其从总线接收数据，该总线将系统存储器耦合到微处理器以及复用和转发逻辑。当存储指令产生微处理器的指令高速缓存的未命中时，不仅将存储结果写入用于更新缓存的缓冲器，而且还写入缓冲器之一。由存储器未命中所涉及的丢失的高速缓存行被从系统存储器请求，被接收到响应缓冲器中，并与存储结果合并。缓存使用合并的数据进行更新。然而，另外，从响应缓冲器中，满足由流水线下载的加载指令产生的存储结果的存储条件。复用和转发逻辑能够在收到缺失的高速缓存行之前和之后将存储结果从响应缓冲器转发到流水线。

7. 发明授权

US06553473B1 Byte-wise tracking on write allocate 有权
标题翻译：对写入分配进行字节跟踪
公开(公告)号：US06553473B1
公开(公告)日：2003-04-22
申请号：US09539146
申请日：2000-03-30
申请人： Darius D. Gaskins , Rodney E. Hooker
发明人： Darius D. Gaskins , Rodney E. Hooker
IPC分类号： G06F1200
CPC分类号： G06F12/0859 , G06F12/0831
摘要： An apparatus and method within a pipeline microprocessor are provided for allocating a cache line within an internal data cache upon a write miss to the data cache. The that apparatus and method allow data to be written to the allocated cache line before fill data for the allocated cache line is received from external memory over a system bus. The apparatus includes write allocate logic and a write buffer. The write allocate logic allocates the cache line within the data cache, it stores data corresponding to the write miss within the allocated cache line, and queues a speculative write command directing an external bus to store said the data to the external memory in the event that transfer of the fill data is interrupted. The speculative write command is stored in the write buffer and, in the event of an interruption such as a bus snoop to the allocated cache line, the write buffer issues the speculative write command to the system bus, thereby writing the data to external memory. When the fill data is received from the system bus, it is filtered by byte-wise tracking logic such that only bytes positions which have not been written during the interim are updated in the allocated cache line.
摘要翻译：提供流水线微处理器内的装置和方法，用于在数据高速缓冲存储器写入错误时，在内部数据高速缓存中分配高速缓存行。该装置和方法允许在经由系统总线从外部存储器接收所分配的高速缓存行的填充数据之前将数据写入分配的高速缓存行。该装置包括写分配逻辑和写缓冲器。写分配逻辑在数据高速缓存中分配高速缓存行，它将与写入未命中对应的数据存储在所分配的高速缓存行内，并排队指示外部总线的推测写入命令，以将数据存储在外部存储器中，填写数据的传送被中断。写入缓冲器中存储推测写入命令，并且在诸如总线监视到分配的高速缓存行的中断的情况下，写入缓冲区向系统总线发出推测写入命令，从而将数据写入外部存储器。当从系统总线接收到填充数据时，它通过逐字跟踪逻辑进行过滤，使得仅在分配的高速缓存行中仅更新了在临时期间尚未写入的字节位置。

8. 发明授权

US06549985B1 Method and apparatus for resolving additional load misses and page table walks under orthogonal stalls in a single pipeline processor 有权
标题翻译：用于解决单个流水线处理器中的正交失速下的额外加载缺失和页表行进的方法和装置
公开(公告)号：US06549985B1
公开(公告)日：2003-04-15
申请号：US09538304
申请日：2000-03-30
申请人： Darius D. Gaskins , G. Glenn Henry , Rodney E. Hooker
发明人： Darius D. Gaskins , G. Glenn Henry , Rodney E. Hooker
IPC分类号： G06F1200
CPC分类号： G06F9/3863 , G06F9/3824 , G06F9/3867 , G06F12/0855 , G06F12/0862 , G06F12/1027
摘要： A data cache in an in-order single-issue microprocessor that detects cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor bus for the missing data so as to overlap with resolution of the stalled instruction, which may also be a cache miss, is provided. The data cache has pipeline stages that parallel portions of the main pipeline in the microprocessor. The data cache employs replay buffers to save the state, i.e., instructions and associated data addresses, of the parallel data cache stages so that instructions above the stalled instruction can continue to proceed down through the data cache and access the cache memory to generate cache misses. The data cache restores the data cache pipeline stages upon detection that stall will terminate. The data cache also detects TLB misses generated by instructions subsequent to the stalled instruction and overlaps page table walks with the stall resolution.
摘要翻译：一个按顺序的单一发行微处理器的数据高速缓存，用于检测由微处理器流水线中的停滞指令后面的指令产生的高速缓存未命中，并且在处理器总线上发出缺失数据的存储器请求，以便与停滞的指令的分辨率重叠，这也可能是缓存未命中。数据缓存具有在微处理器中平行主流水线部分的流水线级。数据高速缓存使用重放缓冲器来保存并行数据高速缓存级的状态即指令和相关联的数据地址，使得停止的指令之上的指令可以继续向下通过数据高速缓存并访问高速缓冲存储器以产生高速缓存未命中。数据高速缓存在检测到停止将终止时恢复数据高速缓存流水线阶段。数据高速缓存还检测到在停止的指令之后的指令产生的TLB未命中，并且与停顿分辨率重叠页表行走。

9. 发明授权

US09952875B2 Microprocessor with ALU integrated into store unit 有权
公开(公告)号：US09952875B2
公开(公告)日：2018-04-24
申请号：US12609193
申请日：2009-10-30
申请人： Gerard M. Col , Colin Eddy , Rodney E. Hooker
发明人： Gerard M. Col , Colin Eddy , Rodney E. Hooker
IPC分类号： G06F9/312 , G06F9/38 , G06F9/30 , G06F12/0875
CPC分类号： G06F9/3875 , G06F9/3001 , G06F9/3004 , G06F9/30043 , G06F9/30145 , G06F9/3017 , G06F9/3893 , G06F12/0875
摘要： A superscalar pipelined microprocessor includes a register set defined by an instruction set architecture of the microprocessor, execution units, and a store unit, coupled to the cache memory and distinct from the other execution units of the microprocessor. The store unit comprises an ALU. The store unit receives an instruction that specifies a source register of the register set and an operation to be performed on a source operand to generate a result. The store unit reads the source operand from the source register. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The store unit operatively writes the result to the cache memory.

10. 发明授权

US09317288B2 Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline 有权
标题翻译：执行x86 ISA和ARM ISA机器语言程序指令的多核微处理器通过硬件转换为由通用执行管道执行的微指令
公开(公告)号：US09317288B2
公开(公告)日：2016-04-19
申请号：US13412904
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30 , G06F9/44
CPC分类号： G06F9/30174 , G06F9/30025 , G06F9/30076 , G06F9/30101 , G06F9/30123 , G06F9/3017 , G06F9/30189 , G06F9/4401
摘要： A microprocessor includes a plurality of processing cores each including a hardware instruction translator that translates instructions of x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs into microinstructions defined by a microinstruction set of the microprocessor. The microinstructions are encoded in a distinct manner from the manner in which the instructions of the x86 and ARM instruction sets are defined. Each core includes an execution pipeline that executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. Each core uses and associated indicator to determine whether it will boot as an x86 ISA core or an ARM ISA core when reset. The indicators are configurable to indicate that at least one of the cores will boot as an x86 ISA core and at least one other of the cores will boot as an ARM ISA core.
摘要翻译：微处理器包括多个处理核心，每个处理核心包括将x86指令集架构（ISA）机器语言程序和高级RISC机器（ARM）ISA机器语言程序的指令转换成由微处理器的微指令集定义的微指令的硬件指令转换器。微指令以与定义x86和ARM指令集的指令的方式不同的方式进行编码。每个内核都包含一个执行管道，执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。每个核心使用和相关联的指示器来确定在重置时是否将引导为x86 ISA内核或ARM ISA内核。这些指示符是可配置的，表示至少有一个内核将作为x86 ISA内核引导，并且至少另外一个内核将作为ARM ISA内核引导。

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