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1. 发明授权

US08281185B2 Advice-based feedback for transactional execution 有权
标题翻译：基于咨询的事务执行反馈
公开(公告)号：US08281185B2
公开(公告)日：2012-10-02
申请号：US12494934
申请日：2009-06-30
申请人： Daniel S. Nussbaum , David Dice , Martin Karlsson , Mark S. Moir
发明人： Daniel S. Nussbaum , David Dice , Martin Karlsson , Mark S. Moir
IPC分类号： G06F11/00
CPC分类号： G06F11/141 , G06F9/3004 , G06F9/30087 , G06F9/30123 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F9/467 , G06F11/0766 , G06F11/0793
摘要： One embodiment provides a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system. During operation, the system records a failure state of the transaction during execution of the transaction using hardware transactional memory mechanisms. Next, the system detects a transaction failure associated with the transaction. Finally, the system provides an advice state associated with the recorded failure state to the program to facilitate a response to the transaction failure by the program.
摘要翻译：一个实施例提供了一种便于在硬件支持的事务存储器系统中执行程序的事务的系统。在操作期间，系统使用硬件事务存储器机制在执行事务期间记录事务的故障状态。接下来，系统检测与事务相关联的事务失败。最后，系统向程序提供与记录的故障状态相关联的建议状态，以便于程序对事务失败的响应。

2. 发明授权

US08225139B2 Facilitating transactional execution through feedback about misspeculation 有权
标题翻译：通过关于错配的反馈促进交易执行
公开(公告)号：US08225139B2
公开(公告)日：2012-07-17
申请号：US12493447
申请日：2009-06-29
申请人： Daniel S. Nussbaum , David Dice , Martin Karlsson , Mark S. Moir
发明人： Daniel S. Nussbaum , David Dice , Martin Karlsson , Mark S. Moir
IPC分类号： G06F9/00
CPC分类号： G06F9/30087 , G06F9/3842 , G06F9/3865 , G06F12/0817
摘要： One embodiment provides a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system. During operation, the system records a misspeculation indicator of the transaction during execution of the transaction using hardware transactional memory mechanisms. Next, the system detects a transaction failure associated with the transaction. Finally, the system provides the recorded misspeculation indicator to the program to facilitate a response to the transaction failure by the program.
摘要翻译：一个实施例提供了一种便于在硬件支持的事务存储器系统中执行程序的事务的系统。在操作期间，系统使用硬件事务存储器机制在执行事务期间记录事务的错误指示符。接下来，系统检测与事务相关联的事务失败。最后，系统向程序提供记录的错误指示符，以便程序响应交易失败。

3. 发明授权

US09367363B2 System and method for integrating best effort hardware mechanisms for supporting transactional memory 有权
标题翻译：集成用于支持事务性内存的最佳硬件机制的系统和方法
公开(公告)号：US09367363B2
公开(公告)日：2016-06-14
申请号：US12238172
申请日：2008-09-25
申请人： Mark S. Moir , David Dice
发明人： Mark S. Moir , David Dice
IPC分类号： G06F9/46 , G06F9/52
CPC分类号： G06F9/52 , G06F9/467
摘要： Systems and methods for integrating multiple best effort hardware transactional support mechanisms, such as Read Set Monitoring (RSM) and Best Effort Hardware Transactional Memory (BEHTM), in a single transactional memory implementation are described. The best effort mechanisms may be integrated such that the overhead associated with support of multiple mechanisms may be reduced and/or the performance of the resulting transactional memory implementations may be improved over those that include any one of the mechanisms, or an un-integrated collection of multiple such mechanisms. Two or more of the mechanisms may be employed concurrently or serially in a single attempt to execute a transaction, without aborting or retrying the transaction. State maintained or used by a first mechanism may be shared with or transferred to another mechanism for use in execution of the transaction. This transfer may be performed automatically by the integrated mechanisms (e.g., without user, programmer, or software intervention).
摘要翻译：描述了在单个事务存储器实现中集成多个尽力而为的硬件事务支持机制（诸如读集监视（RSM）和最佳努力硬件事务存储器（BEHTM））的系统和方法。可以集成尽力而为的机制，使得可以减少与多个机制的支持相关联的开销，和/或可以提高所产生的事务存储器实现的性能，而不是包括机构中的任何一个或非集成集合的多个这样的机制。可以在不中止或重试事务的情况下，单次尝试同时执行或连续执行两个或多个机制来执行事务。由第一机制维护或使用的状态可以与另一机制共享或转移以用于执行交易。该传送可以由集成机制（例如，没有用户，程序员或软件干预）自动执行。

4. 发明授权

US08826249B2 Method and system for optimizing code for a multi-threaded application 有权
标题翻译：用于优化多线程应用程序代码的方法和系统
公开(公告)号：US08826249B2
公开(公告)日：2014-09-02
申请号：US12708014
申请日：2010-02-18
申请人： David Dice , Virendra J. Marathe , Mark S. Moir
发明人： David Dice , Virendra J. Marathe , Mark S. Moir
IPC分类号： G06F9/45 , G06F9/455
CPC分类号： G06F9/45516 , G06F8/456
摘要： In modern multi-threaded environments, threads often work cooperatively toward providing collective or aggregate throughput for an application as a whole. Optimizing in the small for “thread local” common path latency is often but not always the best approach for a concurrent system composed of multiple cooperating threads. Some embodiments provide a technique for augmenting traditional code emission with thread-aware policies and optimization strategies for a multi-threaded application. During operation, the system obtains information about resource contention between executing threads of the multi-threaded application. The system analyzes the resource contention information to identify regions of the code to be optimized. The system recompiles these identified regions to produce optimized code, which is then stored for subsequent execution.
摘要翻译：在现代多线程环境中，线程通常协同工作，为整个应用程序提供集体或聚合吞吐量。对于“线程本地”公共路径延迟的优化通常并不总是对由多个协作线程组成的并发系统的最佳方法。一些实施例提供了一种用于针对多线程应用程序的线程感知策略和优化策略来增加传统代码排放的技术。在运行期间，系统获取有关多线程应用程序的执行线程之间资源争用的信息。系统分析资源争用信息以识别要优化的代码区域。系统重新编译这些识别的区域以产生优化的代码，然后将其存储用于随后的执行。

5. 发明申请

US20100333093A1 FACILITATING TRANSACTIONAL EXECUTION THROUGH FEEDBACK ABOUT MISSPECULATION 有权
标题翻译：通过关于错误的反馈来促进交易的执行
公开(公告)号：US20100333093A1
公开(公告)日：2010-12-30
申请号：US12493447
申请日：2009-06-29
申请人： Daniel S. Nussbaum , David Dice , Martin Karlsson , Mark S. Moir
发明人： Daniel S. Nussbaum , David Dice , Martin Karlsson , Mark S. Moir
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F9/30087 , G06F9/3842 , G06F9/3865 , G06F12/0817
摘要： One embodiment provides a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system. During operation, the system records a misspeculation indicator of the transaction during execution of the transaction using hardware transactional memory mechanisms. Next, the system detects a transaction failure associated with the transaction. Finally, the system provides the recorded misspeculation indicator to the program to facilitate a response to the transaction failure by the program.
摘要翻译：一个实施例提供了一种便于在硬件支持的事务存储器系统中执行程序的事务的系统。在操作期间，系统使用硬件事务存储器机制在执行事务期间记录事务的错误指示符。接下来，系统检测与事务相关联的事务失败。最后，系统向程序提供记录的错误指示符，以便程序响应交易失败。

6. 发明授权

US07814488B1 Quickly reacquirable locks 有权
标题翻译：快速可取锁
公开(公告)号：US07814488B1
公开(公告)日：2010-10-12
申请号：US10669948
申请日：2003-09-24
申请人： David Dice , Mark S. Moir , William N. Scherer, III
发明人： David Dice , Mark S. Moir , William N. Scherer, III
IPC分类号： G06F9/46 , G06F17/00 , G06F13/00
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087
摘要： Techniques are provided for quickly reacquiring mutual exclusion locks (QRLs), such as in the case in which a single process repeatedly acquires and releases the lock and in which no other process attempts to acquire the same lock. When the first holder of a QRL first acquires the lock, it biases the lock to itself. Bias may be directed in different way or at different times in some realizations. Biasing may involve a one-time compare-and-swap instruction. Thereafter, this bias-holder can reacquire and release the lock free of atomic read-modify-write operations. If a second process attempts to acquire a QRL, then the lock may revert to a “default lock”. Any standard mutual exclusion lock may be used as the default lock. A QRL lock may be reinitialized so that it can be rebiased. Rebiasing may be valuable in the case of migratory data access patterns.
摘要翻译：提供了用于快速重新获取互斥锁（QRL）的技术，例如在单个进程重复获取和释放锁定的情况下，其中没有其他进程尝试获取相同的锁。当QRL的第一个持有者首先获得锁定时，它将锁定偏向自身。在某些实现中，偏差可以以不同的方式或在不同的时间被引导。偏移可能涉及一次一次性的交换和交换指令。此后，该偏置保持器可以重新获取和释放锁，而不需要进行原子读取 - 修改 - 写入操作。如果第二个进程尝试获取QRL，则锁可能会恢复为“默认锁定”。任何标准互斥锁都可用作默认锁。 QRL锁可能会被重新初始化，以便可以重新定义。在迁移数据访问模式的情况下，重做可能是有价值的。

7. 发明申请

US20090282386A1 System and Method for Utilizing Available Best Effort Hardware Mechanisms for Supporting Transactional Memory 有权
标题翻译：使用可用的支持事务性存储器的最佳努力硬件机制的系统和方法
公开(公告)号：US20090282386A1
公开(公告)日：2009-11-12
申请号：US12250409
申请日：2008-10-13
申请人： Mark S. Moir , David Dice
发明人： Mark S. Moir , David Dice
IPC分类号： G06F9/44
CPC分类号： G06F9/466
摘要： Systems and methods for managing divergence of best effort transactional support mechanisms in various transactional memory implementations using a portable transaction interface are described. This interface may be implemented by various combinations of best effort hardware features, including none at all. Because the features offered by this interface may be best effort, a default (e.g., software) implementation may always be possible without the need for special hardware support. Software may be written to the interface, and may be executable on a variety of platforms, taking advantage of best effort hardware features included on each one, while not depending on any particular mechanism. Multiple implementations of each operation defined by the interface may be included in one or more portable transaction interface libraries. Systems and/or application software may be written as platform-independent and/or portable, and may call functions of these libraries to implement the operations for a targeted execution environment.
摘要翻译：描述了使用便携式事务接口来管理各种事务存储器实现中的尽力而为事务支持机制的分歧的系统和方法。该接口可以通过尽力而为的硬件特征的各种组合来实现，包括根本没有。由于此接口提供的功能可能是最大的努力，默认（例如，软件）实现可能始终是可能的，而不需要特殊的硬件支持。可以将软件写入接口，并且可以在各种平台上执行，利用包括在每个平台上的尽力而为的硬件特征，而不依赖于任何特定的机制。由接口定义的每个操作的多个实现可以包括在一个或多个便携式事务接口库中。系统和/或应用软件可以被写为独立于平台的和/或可移植的，并且可以调用这些库的功能来实现针对性的执行环境的操作。

8. 发明授权

US09021502B2 Method and system for inter-thread communication using processor messaging 有权
标题翻译：使用处理器消息传递的线程间通信的方法和系统
公开(公告)号：US09021502B2
公开(公告)日：2015-04-28
申请号：US12345179
申请日：2008-12-29
申请人： David Dice , Mark S. Moir
发明人： David Dice , Mark S. Moir
IPC分类号： G06F3/00 , G06F9/46 , G06F9/54 , G06F9/30
CPC分类号： G06F9/466 , G06F9/3009 , G06F9/544
摘要： In shared-memory computer systems, threads may communicate with one another using shared memory. A receiving thread may poll a message target location repeatedly to detect the delivery of a message. Such polling may cause excessive cache coherency traffic and/or congestion on various system buses and/or other interconnects. A method for inter-processor communication may reduce such bus traffic by reducing the number of reads performed and/or the number of cache coherency messages necessary to pass messages. The method may include a thread reading the value of a message target location once, and determining that this value has been modified by detecting inter-processor messages, such as cache coherence messages, indicative of such modification. In systems that support transactional memory, a thread may use transactional memory primitives to detect the cache coherence messages. This may be done by starting a transaction, reading the target memory location, and spinning until the transaction is aborted.
摘要翻译：在共享内存计算机系统中，线程可以使用共享内存彼此进行通信。接收线程可以重复轮询消息目标位置以检测消息的传递。这种轮询可能导致各种系统总线和/或其他互连上的高速缓存一致性业务和/或拥塞。用于处理器间通信的方法可以通过减少执行的读取的数量和/或传递消息所需的高速缓存一致性消息的数量来减少这种总线流量。该方法可以包括读取消息目标位置的值一次的线程，并且通过检测指示这种修改的处理器间消息（例如高速缓存一致性消息）来确定该值已被修改。在支持事务内存的系统中，线程可以使用事务存储器原语来检测高速缓存一致性消息。这可以通过启动事务，读取目标内存位置和旋转直到事务中止来完成。

9. 发明授权

US08776063B2 Method and system for hardware feedback in transactional memory 有权
标题翻译：事务性存储器中硬件反馈的方法和系统
公开(公告)号：US08776063B2
公开(公告)日：2014-07-08
申请号：US12324109
申请日：2008-11-26
申请人： David Dice , Kevin E. Moore , Mark S. Moir
发明人： David Dice , Kevin E. Moore , Mark S. Moir
IPC分类号： G06F9/46 , G06F13/00 , G06F13/28 , G06F9/48
CPC分类号： G06F9/466 , G06F9/467 , G06F9/4843 , G06F9/4881 , G06F12/0815
摘要： Multi-threaded, transactional memory systems may allow concurrent execution of critical sections as speculative transactions. These transactions may abort due to contention among threads. Hardware feedback mechanisms may detect information about aborts and provide that information to software, hardware, or hybrid software/hardware contention management mechanisms. For example, they may detect occurrences of transactional aborts or conditions that may result in transactional aborts, and may update local readable registers or other storage entities (e.g., performance counters) with relevant contention information. This information may include identifying data (e.g., information outlining abort relationships between the processor and other specific physical or logical processors) and/or tallied data (e.g., values of event counters reflecting the number of aborted attempts by the current thread or the resources consumed by those attempts). This contention information may be accessible by contention management mechanisms to inform contention management decisions (e.g. whether to revert transactions to mutual exclusion, delay retries, etc.).
摘要翻译：多线程事务内存系统可允许将关键部分作为投机事务并发执行。这些事务可能由于线程之间的争用而中止。硬件反馈机制可以检测关于中止的信息，并将该信息提供给软件，硬件或混合软件/硬件争用管理机制。例如，它们可以检测可能导致事务中止的事务中止或条件的发生，并且可以用相关争用信息来更新本地可读寄存器或其他存储实体（例如，性能计数器）。该信息可以包括识别数据（例如，概述处理器与其他特定物理或逻辑处理器之间的中止关系的信息）和/或计数数据（例如，反映当前线程的中止尝试次数或消耗的资源的事件计数器的值通过这些尝试）。该争用信息可以通过争用管理机制来访问，以通知争用管理决策（例如，是否将交易恢复为互斥，延迟重试等）。

10. 发明授权

US08560816B2 System and method for performing incremental register checkpointing in transactional memory 有权
标题翻译：用于在事务性存储器中执行增量寄存器检查点的系统和方法
公开(公告)号：US08560816B2
公开(公告)日：2013-10-15
申请号：US12827842
申请日：2010-06-30
申请人： Mark S. Moir , David Dice , Daniel S. Nussbaum , James R. Goodman
发明人： Mark S. Moir , David Dice , Daniel S. Nussbaum , James R. Goodman
IPC分类号： G06F9/00
CPC分类号： G06F9/3863 , G06F9/3834 , G06F9/3859
摘要： Systems and methods described herein for performing incremental register checkpointing may employ a special register to indicate which registers have already been checkpointed. This register may include one bit per register. These systems may also include a special pointer register whose value identifies a location in user memory or in dedicated on-chip storage at which a copy of a register's value should be saved by a checkpointing operation. Only registers modified during speculative execution or execution of a transaction may be checkpointed (e.g., when register modifying instructions are encountered) and subsequently restored (e.g., due to misspeculation or transaction abort), rather than all of the registers of the processor. Each register may be checkpointed at most once for a given speculative episode or atomic transaction. Setting a bit in the special register may prevent checkpointing of the corresponding register. Setting all of the bits in the special register may disable checkpointing.
摘要翻译：本文描述的用于执行增量寄存器检查点的系统和方法可以使用特殊寄存器来指示哪些寄存器已经被检查点。该寄存器可以包括每个寄存器一位。这些系统还可以包括特殊的指针寄存器，其特征指针寄存器的值标识用户存储器中的位置或专用片上存储器，通过检查点操作应该保存寄存器值的副本。只有在推测性执行或执行交易期间修改的寄存器可以是检查点（例如，当遇到寄存器修改指令时）并且随后恢复（例如，由于错误设置或事务中止）而不是处理器的所有寄存器。对于给定的投机事件或原子事务，每个寄存器最多可以被检查点一次。在特殊寄存器中设置一位可能会阻止相应寄存器的检查点。设置特殊寄存器中的所有位可能会禁用检查点。

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