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    • 5. 发明授权
    • Checksum verification accelerator
    • 校验和验证加速器
    • US08726132B2
    • 2014-05-13
    • US13302688
    • 2011-11-22
    • Francois AbelClaude BassoJean L. CalvignacNatarajan VaidhyanathanFabrice Jean Verplanken
    • Francois AbelClaude BassoJean L. CalvignacNatarajan VaidhyanathanFabrice Jean Verplanken
    • H03M13/00
    • H04L1/0079H04L1/0061H04L1/0072
    • Disclosed is a method and system for validating a data packet by a network processor supporting a first network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet; identifies a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The system produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The system validates the data packet by comparing the data packet checksum to the second checksum.
    • 公开了一种用于通过支持第一网络协议和第二网络协议的网络处理器来验证数据分组并利用共享硬件的方法和系统。 网络处理器接收数据包; 识别数据包的网络包协议; 并根据网络分组协议对数据分组进行处理,包括:以第一网络协议特有的第一部分分组长度更新第一寄存器; 用第二网络协议特有的第二部分分组长度更新第二寄存器; 以及用独立于网络协议的字段计算的具有第一校验和的更新第三寄存器。 该系统利用组合来自第一寄存器,第二寄存器和第三寄存器的值的函数产生第二校验和。 系统通过将数据包校验和与第二个校验和进行比较来验证数据包。
    • 6. 发明授权
    • Bidirectional packet flow transformation
    • 双向分组流转换
    • US08619782B2
    • 2013-12-31
    • US13325624
    • 2011-12-14
    • Claude BassoJean L CalvignacNatarajan VaidhyanathanFabrice Verplanken
    • Claude BassoJean L CalvignacNatarajan VaidhyanathanFabrice Verplanken
    • H04L12/28H04L12/56G06F7/00G06F17/00
    • H04L29/0653H04L45/50H04L47/2441
    • A network packet includes a packet key that includes one or more source-destination field pairs that each include a source field and a destination field. For each selected source-destination field pair, first and second sections are selected in the packet key. A source field value is extracted from the source field and a destination field value is extracted from the destination field. For each source bit of the source field value: a destination bit is selected from the destination field; an OR logic function is applied to the source bit and the destination bit to generate a first resulting value is stored at the same bit position as the source bit in the first section; an AND logic function is applied to the source bit and the destination bit to generate a second resulting value stored at the same bit position as the source bit in the second section.
    • 网络分组包括分组密钥,其包括一个或多个源 - 目的地字段对,每个源对目的字段对都包括源字段和目的地字段。 对于每个选择的源 - 目的地字段对,在分组密钥中选择第一和第二部分。 从源字段提取源字段值,并从目标字段提取目的字段值。 对于源字段值的每个源位:从目标字段中选择目标位; 将OR逻辑功能应用于源位,并将目标位产生为第一结果值,存储在与第一段中的源位相同的位位置; 将AND逻辑功能应用于源位和目标位,以产生存储在与第二部分中的源位相同的位位置处的第二个结果值。
    • 9. 发明申请
    • Host Ethernet Adapter for Handling Both Endpoint and Network Node Communications
    • 用于处理端点和网络节点通信的主机以太网适配器
    • US20120192190A1
    • 2012-07-26
    • US13011663
    • 2011-01-21
    • Claude BassoJean L. CalvignacChih-jen ChangPhilippe DamonNatarajan VaidhyanathanFabrice J. VerplankenColin B. Verrilli
    • Claude BassoJean L. CalvignacChih-jen ChangPhilippe DamonNatarajan VaidhyanathanFabrice J. VerplankenColin B. Verrilli
    • G06F9/46
    • G06F15/1735
    • A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode. The method comprises operatively coupling an Ethernet adapter to a multi-core processor system via a processor bus, selectively assigning a first plurality of packets to a first queue pair for servicing in an endpoint mode, running a device driver on the multi-core processing system, the device driver controlling the servicing of the first queue pair by dispatching the first plurality of packets to only one processor core of the multi-core processor system, selectively assigning a second plurality of packets to a second queue pair for servicing in a network node mode; and the Ethernet adapter controlling the servicing of the second queue pair by dispatching the second plurality of packets to multiple processor threads.
    • 提供主机以太网适配器(HEA)和管理网络通信的方法。 HEA包括被配置为通过处理器总线与多核处理器进行通信的主机接口。 所述主机接口包括接收处理元件,所述接收处理元件包括接收处理器,接收缓冲器和用于从所述接收缓冲器向所述接收处理器分发分组的调度器; 包括发送处理器和发送缓冲器的发送处理元件; 以及用于从完成队列(CQ)的头部将网络节点模式中的多核处理器的线程调度完成队列元素(CQE)的完成队列调度器(CQS)。 该方法包括经由处理器总线可操作地将以太网适配器耦合到多核处理器系统,选择性地将第一多个分组分配到第一队列对以在端点模式下进行服务,在多核处理系统上运行设备驱动程序 所述设备驱动程序通过将所述第一多个分组分派到所述多核处理器系统的一个处理器核心来控制所述第一队列对的服务,选择性地将第二多个分组分配给第二队列对以在网络节点中进行服务 模式; 以及所述以太网适配器通过将所述第二多个分组分派到多个处理器线程来控制所述第二队列对的服务。