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    • 7. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    • 半导体存储器件及其操作方法
    • US20130336069A1
    • 2013-12-19
    • US13601448
    • 2012-08-31
    • Do Young KIM
    • Do Young KIM
    • G11C16/34G11C16/04G11C16/12
    • G11C16/3459
    • The present disclosure relates to a semiconductor device and a method of operating the semiconductor device, and particularly to a semiconductor memory device including a memory cell array and a method of operating the semiconductor memory device. The memory device includes a memory cell array including a plurality of memory cells; and a peripheral circuit configured to program a selected memory cell into a target program state, wherein the peripheral circuit performs a program operation by applying a bit line voltage determined according to the threshold voltage to a bit line of the selected memory cell when a threshold voltage of the selected memory cell is higher than a first verification voltage and is lower than a second verification voltage.
    • 本公开涉及半导体器件和操作该半导体器件的方法,特别涉及一种包括存储单元阵列的半导体存储器件以及操作该半导体存储器件的方法。 该存储装置包括一包括多个存储单元的存储单元阵列; 以及周边电路,被配置为将所选择的存储器单元编程为目标编程状态,其中,当阈值电压为阈值电压时,外围电路通过将根据阈值电压确定的位线电压施加到所选存储单元的位线来执行编程操作 所选择的存储单元高于第一验证电压并且低于第二验证电压。
    • 10. 发明申请
    • METHOD AND APPARATUS FOR CONTROLLING DIRECT MEMORY ACCESS
    • 用于控制直接存储器访问的方法和装置
    • US20080133793A1
    • 2008-06-05
    • US11932718
    • 2007-10-31
    • In Ki HWANGWoo Sug JUNGDo Young KIM
    • In Ki HWANGWoo Sug JUNGDo Young KIM
    • G06F13/14H04M1/65
    • G06F13/32
    • Provided are a method and apparatus for controlling direct memory access. In the method, data to be transmitted are read and stored in response to a direct memory access controller (DMAC) operation request, and a portion of the data corresponding to an initial burst size is first transmitted to a data destination. After resetting a burst size according to a state of the data destination, another portion of the data corresponding to the reset burst size is second-transmitted to the data destination. If all the data are not transmitted through the first-transmission and the second-transmission, the second-transmission is repeated until all the data are transmitted. If all the data are transmitted through the first-transmission and the second-transmission, an interrupt signal is generated. Therefore, interrupt signals can be less generated, and thus the processor can access an external memory less frequently, thereby increasing system performance.
    • 提供了一种用于控制直接存储器访问的方法和装置。 在该方法中,响应于直接存储器访问控制器(DMAC)操作请求来读取和存储要发送的数据,并且首先将与初始突发大小相对应的数据的一部分发送到数据目的地。 在根据数据目的地的状态复位突发大小之后,与复位突发大小对应的数据的另一部分被第二次发送到数据目的地。 如果所有的数据都不是通过第一次传输和第二次传输传输的,那么重复第二次传输,直到所有的数据被发送。 如果通过第一次传输和第二次传输传输所有数据,则产生一个中断信号。 因此,可以较少地产生中断信号,因此处理器可以较少地访问外部存储器,从而提高系统性能。